luke
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Cleanup

This commit is contained in:
Miodrag Milanovic 2026-03-26 08:14:16 +01:00
parent bfd3e150fa
commit 76732497b9
8 changed files with 75 additions and 76 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
tests/aiger/generate_mk.py
View File

@ -11,6 +11,9 @@ import os
def base(fn): def base(fn):
return os.path.splitext(fn)[0] return os.path.splitext(fn)[0]
def cmd(lines):
return " \\\n".join(lines)
# NB: *.aag and *.aig must contain a symbol table naming the primary # NB: *.aag and *.aig must contain a symbol table naming the primary
# inputs and outputs, otherwise ABC and Yosys will name them # inputs and outputs, otherwise ABC and Yosys will name them
# arbitrarily (and inconsistently with each other). # arbitrarily (and inconsistently with each other).
@ -24,7 +27,7 @@ def create_tests():
for aag in aags: for aag in aags:
b = base(aag) b = base(aag)
cmd = [ gen_tests_makefile.generate_target(aag, cmd([
f"$(ABC) -q \"read -c {b}.aig; write {b}_ref.v\";", f"$(ABC) -q \"read -c {b}.aig; write {b}_ref.v\";",
"$(YOSYS) -qp \"", "$(YOSYS) -qp \"",
f"read_verilog {b}_ref.v;", f"read_verilog {b}_ref.v;",
@ -38,20 +41,18 @@ def create_tests():
"miter -equiv -flatten -make_assert -make_outputs gold gate miter;", "miter -equiv -flatten -make_assert -make_outputs gold gate miter;",
"sat -verify -prove-asserts -show-ports -seq 16 miter;", "sat -verify -prove-asserts -show-ports -seq 16 miter;",
f"\" -l {aag}.log" f"\" -l {aag}.log"
] ]))
gen_tests_makefile.generate_cmd_test(aag, cmd)
# ---- Yosys script tests ---- # ---- Yosys script tests ----
for ys in yss: for ys in yss:
gen_tests_makefile.generate_ys_test(ys) gen_tests_makefile.generate_ys_test(ys)
cmd = [ "rm -rf gate; mkdir gate;", gen_tests_makefile.generate_target("aigmap", cmd([
"$(YOSYS) --no-version -p \"test_cell -aigmap -w gate/ -n 1 -s 1 all\";", "rm -rf gate; mkdir gate;",
"set -o pipefail; diff --brief gold gate | tee aigmap.err;", "$(YOSYS) --no-version -p \"test_cell -aigmap -w gate/ -n 1 -s 1 all\";",
"rm -f aigmap.err" ] "set -o pipefail; diff --brief gold gate | tee aigmap.err;",
"rm -f aigmap.err"
gen_tests_makefile.generate_cmd_test("aigmap", cmd) ]))
extra = [ f"ABC ?= {gen_tests_makefile.yosys_basedir}/yosys-abc", "SHELL := /bin/bash" ] extra = [ f"ABC ?= {gen_tests_makefile.yosys_basedir}/yosys-abc", "SHELL := /bin/bash" ]

4
tests/cxxrtl/generate_mk.py
View File

@ -7,13 +7,13 @@ import gen_tests_makefile
def run_subtest(name): def run_subtest(name):
gen_tests_makefile.generate_cmd_test(f"cxxrtl_{name}", [ gen_tests_makefile.generate_cmd_test(f"cxxrtl_{name}", [
f"$${{CXX:-g++}} -std=c++11 -O2 -o cxxrtl-test-{name} -I../../backends/cxxrtl/runtime test_{name}.cc -lstdc++;", f"$${{CXX:-g++}} -std=c++11 -O2 -o cxxrtl-test-{name} -I../../backends/cxxrtl/runtime test_{name}.cc -lstdc++",
f"./cxxrtl-test-{name}", f"./cxxrtl-test-{name}",
]) ])
def compile_only(): def compile_only():
gen_tests_makefile.generate_cmd_test("cxxrtl_unconnected_output", [ gen_tests_makefile.generate_cmd_test("cxxrtl_unconnected_output", [
'$(YOSYS) -p "read_verilog test_unconnected_output.v; select =*; proc; clean; write_cxxrtl cxxrtl-test-unconnected_output.cc";', '$(YOSYS) -p "read_verilog test_unconnected_output.v; select =*; proc; clean; write_cxxrtl cxxrtl-test-unconnected_output.cc"',
f'$${{CXX:-g++}} -std=c++11 -c -o cxxrtl-test-unconnected_output -I../../backends/cxxrtl/runtime cxxrtl-test-unconnected_output.cc', f'$${{CXX:-g++}} -std=c++11 -c -o cxxrtl-test-unconnected_output -I../../backends/cxxrtl/runtime cxxrtl-test-unconnected_output.cc',
]) ])

27
tests/fmt/generate_mk.py
View File

@ -5,16 +5,13 @@ sys.path.append("..")
import gen_tests_makefile import gen_tests_makefile
def cmd(lines):
return " && \\\n".join(lines)
def initial_display(): def initial_display():
gen_tests_makefile.generate_target("initial_display", cmd([ gen_tests_makefile.generate_cmd_test("initial_display", [
f"$(YOSYS) -p \"read_verilog initial_display.v\" | awk '/<<<BEGIN>>>/,/<<<END>>>/ {{print $$0}}' >yosys-initial_display.log 2>&1", f"$(YOSYS) -p \"read_verilog initial_display.v\" | awk '/<<<BEGIN>>>/,/<<<END>>>/ {{print $$0}}' >yosys-initial_display.log 2>&1",
"iverilog -o iverilog-initial_display initial_display.v", "iverilog -o iverilog-initial_display initial_display.v",
"./iverilog-initial_display >iverilog-initial_display.log", "./iverilog-initial_display >iverilog-initial_display.log",
"diff yosys-initial_display.log iverilog-initial_display.log", "diff yosys-initial_display.log iverilog-initial_display.log",
])) ])
def always_display(): def always_display():
@ -28,11 +25,11 @@ def always_display():
] ]
for name, defs in cases: for name, defs in cases:
gen_tests_makefile.generate_target(f"always_display_{name}", cmd([ gen_tests_makefile.generate_cmd_test(f"always_display_{name}", [
f"$(YOSYS) -p \"read_verilog {defs} always_display.v; proc; opt_expr -mux_bool; clean\" -o yosys-always_display-{name}-1.v", f"$(YOSYS) -p \"read_verilog {defs} always_display.v; proc; opt_expr -mux_bool; clean\" -o yosys-always_display-{name}-1.v",
f"$(YOSYS) -p \"read_verilog yosys-always_display-{name}-1.v; proc; opt_expr -mux_bool; clean\" -o yosys-always_display-{name}-2.v", f"$(YOSYS) -p \"read_verilog yosys-always_display-{name}-1.v; proc; opt_expr -mux_bool; clean\" -o yosys-always_display-{name}-2.v",
f"diff yosys-always_display-{name}-1.v yosys-always_display-{name}-2.v", f"diff yosys-always_display-{name}-1.v yosys-always_display-{name}-2.v",
])) ])
def roundtrip(): def roundtrip():
@ -48,7 +45,7 @@ def roundtrip():
] ]
for name, defs in cases: for name, defs in cases:
gen_tests_makefile.generate_target(f"roundtrip_{name}", cmd([ gen_tests_makefile.generate_cmd_test(f"roundtrip_{name}", [
f"$(YOSYS) -p \"read_verilog {defs} roundtrip.v; proc; clean\" -o yosys-roundtrip-{name}-1.v", f"$(YOSYS) -p \"read_verilog {defs} roundtrip.v; proc; clean\" -o yosys-roundtrip-{name}-1.v",
f"$(YOSYS) -p \"read_verilog yosys-roundtrip-{name}-1.v; proc; clean\" -o yosys-roundtrip-{name}-2.v", f"$(YOSYS) -p \"read_verilog yosys-roundtrip-{name}-1.v; proc; clean\" -o yosys-roundtrip-{name}-2.v",
f"diff yosys-roundtrip-{name}-1.v yosys-roundtrip-{name}-2.v", f"diff yosys-roundtrip-{name}-1.v yosys-roundtrip-{name}-2.v",
@ -64,14 +61,14 @@ def roundtrip():
f"diff iverilog-roundtrip-{name}.log iverilog-roundtrip-{name}-1.log", f"diff iverilog-roundtrip-{name}.log iverilog-roundtrip-{name}-1.log",
f"diff iverilog-roundtrip-{name}-1.log iverilog-roundtrip-{name}-2.log", f"diff iverilog-roundtrip-{name}-1.log iverilog-roundtrip-{name}-2.log",
])) ])
def cxxrtl(): def cxxrtl():
cases = ["always_full", "always_comb"] cases = ["always_full", "always_comb"]
for name in cases: for name in cases:
gen_tests_makefile.generate_target(f"cxxrtl_{name}", cmd([ gen_tests_makefile.generate_cmd_test(f"cxxrtl_{name}", [
f"$(YOSYS) -p \"read_verilog {name}.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-{name}.cc\"", f"$(YOSYS) -p \"read_verilog {name}.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-{name}.cc\"",
f"$${{CXX:-g++}} -std=c++11 -o yosys-{name} -I../../backends/cxxrtl/runtime {name}_tb.cc -lstdc++", f"$${{CXX:-g++}} -std=c++11 -o yosys-{name} -I../../backends/cxxrtl/runtime {name}_tb.cc -lstdc++",
f"./yosys-{name} 2>yosys-{name}.log", f"./yosys-{name} 2>yosys-{name}.log",
@ -80,19 +77,19 @@ def cxxrtl():
f"./iverilog-{name} | grep -v \"$finish called\" >iverilog-{name}.log", f"./iverilog-{name} | grep -v \"$finish called\" >iverilog-{name}.log",
f"diff iverilog-{name}.log yosys-{name}.log", f"diff iverilog-{name}.log yosys-{name}.log",
])) ])
def extra(): def extra():
gen_tests_makefile.generate_target("always_full_equiv", cmd([ gen_tests_makefile.generate_cmd_test("always_full_equiv", [
"$(YOSYS) -p \"read_verilog always_full.v; prep; clean\" -o yosys-always_full-1.v", "$(YOSYS) -p \"read_verilog always_full.v; prep; clean\" -o yosys-always_full-1.v",
"iverilog -o iverilog-always_full-1 yosys-always_full-1.v always_full_tb.v", "iverilog -o iverilog-always_full-1 yosys-always_full-1.v always_full_tb.v",
"./iverilog-always_full-1 > tmp.log", "./iverilog-always_full-1 > tmp.log",
"grep -v '\\$finish called' tmp.log > iverilog-always_full-1.log", "grep -v '\\$finish called' tmp.log > iverilog-always_full-1.log",
"diff iverilog-always_full.log iverilog-always_full-1.log", "diff iverilog-always_full.log iverilog-always_full-1.log",
]), deps=["cxxrtl_always_full"]) ], deps=["cxxrtl_always_full"])
gen_tests_makefile.generate_target("display_lm", cmd([ gen_tests_makefile.generate_cmd_test("display_lm", [
"$(YOSYS) -p \"read_verilog display_lm.v\" >yosys-display_lm.log 2>&1", "$(YOSYS) -p \"read_verilog display_lm.v\" >yosys-display_lm.log 2>&1",
"$(YOSYS) -p \"read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc\"", "$(YOSYS) -p \"read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc\"",
f"$${{CXX:-g++}} -std=c++11 -o yosys-display_lm_cc -I../../backends/cxxrtl/runtime display_lm_tb.cc -lstdc++", f"$${{CXX:-g++}} -std=c++11 -o yosys-display_lm_cc -I../../backends/cxxrtl/runtime display_lm_tb.cc -lstdc++",
@ -101,7 +98,7 @@ def extra():
"grep \"^%m: \\\\\\bot\\$$\" \"yosys-display_lm.log\"", "grep \"^%m: \\\\\\bot\\$$\" \"yosys-display_lm.log\"",
"grep \"^%l: \\\\\\bot\\$$\" \"yosys-display_lm_cc.log\"", "grep \"^%l: \\\\\\bot\\$$\" \"yosys-display_lm_cc.log\"",
"grep \"^%m: \\\\\\bot\\$$\" \"yosys-display_lm_cc.log\"", "grep \"^%m: \\\\\\bot\\$$\" \"yosys-display_lm_cc.log\"",
])) ])
def main(): def main():

6
tests/gen_tests_makefile.py
View File

@ -56,11 +56,11 @@ def unpack_cmd(cmd):
if isinstance(cmd, str): if isinstance(cmd, str):
return cmd return cmd
if isinstance(cmd, (list, tuple)): if isinstance(cmd, (list, tuple)):
return " \\\n".join(cmd) return " && \\\n".join(cmd)
raise TypeError("cmd must be a string or a list/tuple of strings") raise TypeError("cmd must be a string or a list/tuple of strings")
def generate_cmd_test(test_name, cmd, yosys_args=""): def generate_cmd_test(test_name, cmd, yosys_args="", deps = None):
generate_target(test_name, unpack_cmd(cmd)) generate_target(test_name, unpack_cmd(cmd), deps)
def generate_tests(argv, cmds): def generate_tests(argv, cmds):
parser = argparse.ArgumentParser(add_help=False) parser = argparse.ArgumentParser(add_help=False)

13
tests/liberty/generate_mk.py
View File

@ -12,13 +12,13 @@ def lib_tests():
base = os.path.splitext(lib)[0] base = os.path.splitext(lib)[0]
gen_tests_makefile.generate_cmd_test(lib, [ gen_tests_makefile.generate_cmd_test(lib, [
f'$(YOSYS) -p "read_verilog small.v; synth -top small; dfflibmap -info -liberty {lib}" -ql {base}.log;', f'$(YOSYS) -p "read_verilog small.v; synth -top small; dfflibmap -info -liberty {lib}" -ql {base}.log',
f'../../yosys-filterlib - {lib} > {lib}.filtered;', f'$(YOSYS_FILTERLIB) - {lib} > {lib}.filtered',
f'../../yosys-filterlib -verilogsim {lib} > {lib}.verilogsim;', f'$(YOSYS_FILTERLIB) -verilogsim {lib} > {lib}.verilogsim',
f'diff {lib}.filtered {lib}.filtered.ok;', f'diff {lib}.filtered {lib}.filtered.ok',
f'diff {lib}.verilogsim {lib}.verilogsim.ok;', f'diff {lib}.verilogsim {lib}.verilogsim.ok',
f'if [ -e {base}.log.ok ]; then ' f'if [ -e {base}.log.ok ]; then '
f'$(YOSYS) -p "dfflibmap -info -liberty {lib}" -TqqQl {base}.log; ' f'$(YOSYS) -p "dfflibmap -info -liberty {lib}" -TqqQl {base}.log; '
@ -36,7 +36,8 @@ def main():
lib_tests() lib_tests()
ys_tests() ys_tests()
gen_tests_makefile.generate_custom(callback) gen_tests_makefile.generate_custom(callback,
[f"YOSYS_FILTERLIB ?= {gen_tests_makefile.yosys_basedir}/yosys-filterlib"])
if __name__ == "__main__": if __name__ == "__main__":

52
tests/memfile/generate_mk.py
View File

@ -9,59 +9,59 @@ def create_tests():
setup = "mkdir -p temp && cp content1.dat temp/content2.dat" setup = "mkdir -p temp && cp content1.dat temp/content2.dat"
gen_tests_makefile.generate_cmd_test("parent_content1", [ gen_tests_makefile.generate_cmd_test("parent_content1", [
f"{setup};", f"{setup}",
'cd .. && $(YOSYS_ABS) -qp "read_verilog -defer memfile/memory.v;', 'cd .. && $(YOSYS_ABS) -qp "read_verilog -defer memfile/memory.v; '
'chparam -set MEMFILE \\"content1.dat\\" memory"', 'chparam -set MEMFILE \\"content1.dat\\" memory"'
]) ])
gen_tests_makefile.generate_cmd_test("parent_content2_temp", [ gen_tests_makefile.generate_cmd_test("parent_content2_temp", [
f"{setup};", f"{setup}",
'cd .. && $(YOSYS_ABS) -qp "read_verilog -defer memfile/memory.v;', 'cd .. && $(YOSYS_ABS) -qp "read_verilog -defer memfile/memory.v; '
'chparam -set MEMFILE \\"temp/content2.dat\\" memory"', 'chparam -set MEMFILE \\"temp/content2.dat\\" memory"'
]) ])
gen_tests_makefile.generate_cmd_test("parent_content2_full", [ gen_tests_makefile.generate_cmd_test("parent_content2_full", [
f"{setup};", f"{setup}",
'cd .. && $(YOSYS_ABS) -qp "read_verilog -defer memfile/memory.v;', 'cd .. && $(YOSYS_ABS) -qp "read_verilog -defer memfile/memory.v; '
'chparam -set MEMFILE \\"memfile/temp/content2.dat\\" memory"', 'chparam -set MEMFILE \\"memfile/temp/content2.dat\\" memory"'
]) ])
gen_tests_makefile.generate_cmd_test("same_content1", [ gen_tests_makefile.generate_cmd_test("same_content1", [
f"{setup};", f"{setup}",
'$(YOSYS) -qp "read_verilog -defer memory.v;', '$(YOSYS) -qp "read_verilog -defer memory.v; '
'chparam -set MEMFILE \\"content1.dat\\" memory"', 'chparam -set MEMFILE \\"content1.dat\\" memory"'
]) ])
gen_tests_makefile.generate_cmd_test("same_content2", [ gen_tests_makefile.generate_cmd_test("same_content2", [
f"{setup};", f"{setup}",
'$(YOSYS) -qp "read_verilog -defer memory.v;', '$(YOSYS) -qp "read_verilog -defer memory.v; '
'chparam -set MEMFILE \\"temp/content2.dat\\" memory"', 'chparam -set MEMFILE \\"temp/content2.dat\\" memory"'
]) ])
gen_tests_makefile.generate_cmd_test("child_content1", [ gen_tests_makefile.generate_cmd_test("child_content1", [
f"{setup};", f"{setup}",
'cd temp && ../$(YOSYS) -qp "read_verilog -defer ../memory.v;', 'cd temp && ../$(YOSYS) -qp "read_verilog -defer ../memory.v; '
'chparam -set MEMFILE \\"content1.dat\\" memory"', 'chparam -set MEMFILE \\"content1.dat\\" memory"'
]) ])
gen_tests_makefile.generate_cmd_test("child_content2_temp", [ gen_tests_makefile.generate_cmd_test("child_content2_temp", [
f"{setup};", f"{setup}",
'cd temp && ../$(YOSYS) -qp "read_verilog -defer ../memory.v;', 'cd temp && ../$(YOSYS) -qp "read_verilog -defer ../memory.v; '
'chparam -set MEMFILE \\"temp/content2.dat\\" memory"', 'chparam -set MEMFILE \\"temp/content2.dat\\" memory"'
]) ])
gen_tests_makefile.generate_cmd_test("child_content2_direct", [ gen_tests_makefile.generate_cmd_test("child_content2_direct", [
f"{setup};", f"{setup}",
'cd temp && ../$(YOSYS) -qp "read_verilog -defer ../memory.v;', 'cd temp && ../$(YOSYS) -qp "read_verilog -defer ../memory.v; '
'chparam -set MEMFILE \\"temp/content2.dat\\" memory"', 'chparam -set MEMFILE \\"temp/content2.dat\\" memory"'
]) ])
gen_tests_makefile.generate_cmd_test("fail_empty_filename", gen_tests_makefile.generate_cmd_test("fail_empty_filename",
'! $(YOSYS) -qp "read_verilog memory.v"') '! $(YOSYS) -qp "read_verilog memory.v"')
gen_tests_makefile.generate_cmd_test("fail_missing_file", [ gen_tests_makefile.generate_cmd_test("fail_missing_file", [
'! $(YOSYS) -qp "read_verilog -defer memory.v;', '! $(YOSYS) -qp "read_verilog -defer memory.v; '
'chparam -set MEMFILE \\"content3.dat\\" memory"', 'chparam -set MEMFILE \\"content3.dat\\" memory"'
]) ])
extra = ["YOSYS_ABS := $(abspath $(YOSYS))"] extra = ["YOSYS_ABS := $(abspath $(YOSYS))"]

4
tests/realmath/generate_mk.py
View File

@ -100,8 +100,8 @@ for idx in range(args.count):
def create_tests(): def create_tests():
for idx in range(args.count): for idx in range(args.count):
cmd = [ cmd = [
f"$(YOSYS) -qq uut_{idx:05d}.ys &&", f"$(YOSYS) -qq uut_{idx:05d}.ys",
f"iverilog -o uut_{idx:05d}_tb uut_{idx:05d}_tb.v uut_{idx:05d}.v uut_{idx:05d}_syn.v &&", f"iverilog -o uut_{idx:05d}_tb uut_{idx:05d}_tb.v uut_{idx:05d}.v uut_{idx:05d}_syn.v",
f"./uut_{idx:05d}_tb" f"./uut_{idx:05d}_tb"
# f"./uut_{idx:05d}_tb | tee uut_{idx:05d}.err;", # f"./uut_{idx:05d}_tb | tee uut_{idx:05d}.err;",
# f"if test -s uut_{idx:05d}.err; then", # f"if test -s uut_{idx:05d}.err; then",

24
tests/svinterfaces/generate_mk.py
View File

@ -15,18 +15,18 @@ runone_tests = [
def run_one(): def run_one():
for testname in runone_tests: for testname in runone_tests:
cmd_lines = [ cmd_lines = [
f'$(YOSYS) -p "read_verilog -sv {testname}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog {testname}_syn.v" >> {testname}.log_stdout 2>> {testname}.log_stderr;', f'$(YOSYS) -p "read_verilog -sv {testname}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog {testname}_syn.v" >> {testname}.log_stdout 2>> {testname}.log_stderr',
f'$(YOSYS) -p "read_verilog -sv {testname}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog {testname}_ref_syn.v" >> {testname}.log_stdout 2>> {testname}.log_stderr;', f'$(YOSYS) -p "read_verilog -sv {testname}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog {testname}_ref_syn.v" >> {testname}.log_stdout 2>> {testname}.log_stderr',
f'rm -f a.out reference_result.txt dut_result.txt;', f'rm -f a.out reference_result.txt dut_result.txt',
f'iverilog -g2012 {testname}_syn.v;', f'iverilog -g2012 {testname}_syn.v',
f'iverilog -g2012 {testname}_ref_syn.v;', f'iverilog -g2012 {testname}_ref_syn.v',
f'iverilog -g2012 {testname}_tb.v {testname}_ref_syn.v;', f'iverilog -g2012 {testname}_tb.v {testname}_ref_syn.v',
f'./a.out;', f'./a.out',
f'mv output.txt reference_result.txt;', f'mv output.txt reference_result.txt',
f'iverilog -g2012 {testname}_tb_wrapper.v {testname}_syn.v;' if testname=="svinterface_at_top" else f'iverilog -g2012 {testname}_tb_wrapper.v {testname}_syn.v' if testname=="svinterface_at_top" else
f'iverilog -g2012 {testname}_tb.v {testname}_syn.v;', f'iverilog -g2012 {testname}_tb.v {testname}_syn.v',
f'./a.out;', f'./a.out',
f'mv output.txt dut_result.txt;', f'mv output.txt dut_result.txt',
f'diff reference_result.txt dut_result.txt > {testname}.diff', f'diff reference_result.txt dut_result.txt > {testname}.diff',
] ]
gen_tests_makefile.generate_cmd_test(testname, cmd_lines) gen_tests_makefile.generate_cmd_test(testname, cmd_lines)