mirror of https://github.com/YosysHQ/yosys.git
Explicitly pin C_SEL to 0
Co-authored-by: Thomas Vanhaniemi <thomas.vanhaniemi@gmail.com>
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@ -11,6 +11,7 @@ module \$__MUL27X18 (input [26:0] A, input [17:0] B, output [44:0] Y);
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MULTALU27X18 #(
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.MULT12X12_EN("FALSE"),
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.MULT_RESET_MODE("SYNC"),
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.C_SEL(1'b0),
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.AREG_CLK("BYPASS"),
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.BREG_CLK("BYPASS"),
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.PREG_CLK("BYPASS"),
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