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read_aiger to accept empty string for clk_name, passable only if no latches

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Eddie Hung
2019-02-25 15:34:02 -08:00
parent 0ca3fd6a1c
commit 721f6a14fb
2 changed files with 3 additions and 2 deletions
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passes/techmap/abc9.cc
+1 -2
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@@ -523,8 +523,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
bool builtin_lib = liberty_file.empty();
RTLIL::Design *mapped_design = new RTLIL::Design;
//parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode);
buffer = stringf("%s/%s", tempdir_name.c_str(), "input.symbols");
AigerReader reader(mapped_design, ifs, "\\netlist", "\\clk", buffer, true /* wideports */);
AigerReader reader(mapped_design, ifs, "\\netlist", "" /* clk_name */, "" /* map_filename */, true /* wideports */);
reader.parse_xaiger();
ifs.close();