mirror of https://github.com/YosysHQ/yosys.git
opt_merge_inc: re add initvals deletion
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@ -439,7 +439,14 @@ struct OptMergeIncWorker
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for (auto &[port, sig] : cell->connections()) {
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for (auto &[port, sig] : cell->connections()) {
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if (cell->output(port)) {
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if (cell->output(port)) {
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// TODO why was this removed before?
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RTLIL::SigSpec other_sig = other_cell->getPort(port);
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Const init = initvals(other_sig);
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initvals.remove_init(sig);
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initvals.remove_init(other_sig);
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module->connect(sig, other_cell->getPort(port));
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module->connect(sig, other_cell->getPort(port));
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assign_map.add(sig, other_sig);
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initvals.set_init(other_sig, init);
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}
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}
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}
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}
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