verilog: improve specify support when not in -specify mode

tests/various/specify.v

@@ -7,11 +7,9 @@ module test (
 		if (EN) Q <= D;
 
 	specify
-`ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS
 		if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4);
 		$setup(D, posedge CLK &&& EN, 5);
 		$hold(posedge CLK, D &&& EN, 6);
-`endif
 	endspecify
 endmodule
 

tests/various/specify.ys

@@ -55,4 +55,4 @@ equiv_induct -seq 5
 equiv_status -assert
 design -reset
 
-read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v
+read_verilog specify.v