mirror of https://github.com/YosysHQ/yosys.git
Fixes for filtering small cases and catching more larger ones with trickier signatures
This commit is contained in:
Akash Levy
parent
69edb27ab3
commit
6a8d800e63
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@ -64,15 +64,28 @@ struct OptAndOrPmuxWorker
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std::vector<std::vector<DataExpr>> bits;
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};
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struct BitContribs {
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int bit_idx = -1;
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SigSpec select;
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std::vector<Contribution> contribs;
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};
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struct SelectGroup {
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SigSpec select;
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std::vector<BitContribs> bits;
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};
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Module *module;
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SigMap sigmap;
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dict<SigBit, DriverBit> bit_drivers;
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dict<SigBit, std::vector<ConsumerBit>> bit_consumers;
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pool<SigBit> observable_bits;
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pool<Cell*> removed_cells;
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int converted_count = 0;
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static const int max_cone_bits = 100000;
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static const int min_pmux_bits = 8;
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OptAndOrPmuxWorker(Module *module) : module(module), sigmap(module)
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{
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@ -83,6 +96,7 @@ struct OptAndOrPmuxWorker
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{
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bit_drivers.clear();
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bit_consumers.clear();
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observable_bits.clear();
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for (auto cell : module->cells())
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{
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@ -112,6 +126,22 @@ struct OptAndOrPmuxWorker
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}
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}
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}
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for (auto &conn : module->connections())
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{
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SigSpec lhs = conn.first;
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SigSpec rhs = sigmap(conn.second);
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for (int i = 0; i < std::min(GetSize(lhs), GetSize(rhs)); i++) {
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SigBit lhs_bit = lhs[i];
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SigBit rhs_bit = rhs[i];
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if (lhs_bit.wire == nullptr)
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continue;
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if (lhs_bit.wire->port_output || lhs_bit.wire->get_bool_attribute(ID::keep)) {
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observable_bits.insert(lhs_bit);
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observable_bits.insert(rhs_bit);
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}
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}
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}
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}
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bool get_driver(SigBit bit, DriverBit &driver) const
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@ -135,36 +165,20 @@ struct OptAndOrPmuxWorker
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return true;
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}
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bool feeds_or(Cell *cell) const
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bool bit_has_observable_output(SigBit bit) const
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{
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SigSpec y = sigmap(cell->getPort(ID::Y));
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for (auto bit : y) {
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if (bit.wire == nullptr)
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continue;
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auto it = bit_consumers.find(bit);
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if (it == bit_consumers.end())
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continue;
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bit = sigmap(bit);
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if (bit.wire == nullptr)
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return false;
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if (bit.wire->port_output || bit.wire->get_bool_attribute(ID::keep))
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return true;
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if (observable_bits.count(bit))
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return true;
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auto it = bit_consumers.find(bit);
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if (it != bit_consumers.end())
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for (auto &consumer : it->second)
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if (!removed_cells.count(consumer.cell) && consumer.cell != cell && consumer.cell->type == ID($or))
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if (!removed_cells.count(consumer.cell))
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return true;
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}
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return false;
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}
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bool has_observable_output(Cell *cell) const
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{
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SigSpec y = sigmap(cell->getPort(ID::Y));
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for (auto bit : y) {
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if (bit.wire == nullptr)
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continue;
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if (bit.wire->port_output || bit.wire->get_bool_attribute(ID::keep))
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return true;
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auto it = bit_consumers.find(bit);
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if (it != bit_consumers.end())
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for (auto &consumer : it->second)
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if (!removed_cells.count(consumer.cell))
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return true;
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}
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return false;
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}
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@ -358,46 +372,56 @@ struct OptAndOrPmuxWorker
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return make_or_tree(cell, terms, src);
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}
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bool try_convert(Cell *cell)
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bool collect_bit_contribs(Cell *cell, int bit_idx, BitContribs &bit_contribs) const
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{
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if (removed_cells.count(cell))
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return false;
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if (cell->type != ID($or) || cell->get_bool_attribute(ID::keep))
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return false;
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if (feeds_or(cell) || !has_observable_output(cell))
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SigSpec y = sigmap(cell->getPort(ID::Y));
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SigBit y_bit = y[bit_idx];
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if (!bit_has_observable_output(y_bit))
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return false;
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std::vector<SigBit> terms;
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pool<SigBit> seen;
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int budget = max_cone_bits;
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if (!collect_or_terms(y_bit, terms, seen, budget))
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return false;
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bit_contribs.bit_idx = bit_idx;
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for (auto term : terms)
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{
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Contribution contrib;
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TermResult result = parse_term(term, contrib);
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if (result == TERM_ZERO)
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continue;
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if (result == TERM_FAIL)
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return false;
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if (bit_contribs.select.empty())
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bit_contribs.select = contrib.eq.select;
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else if (bit_contribs.select != contrib.eq.select)
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return false;
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bit_contribs.contribs.push_back(contrib);
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}
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return !bit_contribs.contribs.empty();
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}
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bool convert_group(Cell *cell, const SelectGroup &group, pool<int> &converted_bits)
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{
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SigSpec y = sigmap(cell->getPort(ID::Y));
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int width = GetSize(y);
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int width = GetSize(group.bits);
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if (width == 0)
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return false;
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SigSpec select;
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std::vector<Arm> arms;
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dict<Const, int> arm_index;
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for (int bit_idx = 0; bit_idx < width; bit_idx++)
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for (int group_bit_idx = 0; group_bit_idx < width; group_bit_idx++)
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{
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std::vector<SigBit> terms;
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pool<SigBit> seen;
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int budget = max_cone_bits;
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if (!collect_or_terms(y[bit_idx], terms, seen, budget))
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return false;
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for (auto term : terms)
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const BitContribs &bit_contribs = group.bits[group_bit_idx];
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for (auto &contrib : bit_contribs.contribs)
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{
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Contribution contrib;
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TermResult result = parse_term(term, contrib);
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if (result == TERM_ZERO)
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continue;
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if (result == TERM_FAIL)
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return false;
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if (select.empty())
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select = contrib.eq.select;
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else if (select != contrib.eq.select)
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return false;
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int arm_idx;
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auto it = arm_index.find(contrib.eq.value);
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if (it == arm_index.end()) {
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@ -408,16 +432,19 @@ struct OptAndOrPmuxWorker
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arm_idx = it->second;
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}
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arms[arm_idx].bits[bit_idx].push_back(contrib.data);
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arms[arm_idx].bits[group_bit_idx].push_back(contrib.data);
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}
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}
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if (GetSize(arms) < 2)
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if (GetSize(arms) < 2 || GetSize(arms) * width < min_pmux_bits)
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return false;
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SigSpec pmux_s, pmux_b;
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SigSpec pmux_y, pmux_s, pmux_b;
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std::string src = cell->get_src_attribute();
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for (auto &bit_contribs : group.bits)
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pmux_y.append(y[bit_contribs.bit_idx]);
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for (auto &arm : arms)
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{
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SigSpec data;
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@ -431,11 +458,69 @@ struct OptAndOrPmuxWorker
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log("Converting AND/OR mux %s.%s to a $pmux with %d cases and width %d.\n",
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log_id(module), log_id(cell), GetSize(arms), width);
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module->addPmux(NEW_ID2_SUFFIX("andor_pmux"), Const(State::S0, width), pmux_b, pmux_s, cell->getPort(ID::Y), src);
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module->addPmux(NEW_ID2_SUFFIX("andor_pmux"), Const(State::S0, width), pmux_b, pmux_s, pmux_y, src);
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for (auto &bit_contribs : group.bits)
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converted_bits.insert(bit_contribs.bit_idx);
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converted_count++;
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return true;
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}
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bool try_convert(Cell *cell)
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{
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if (removed_cells.count(cell))
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return false;
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if (cell->type != ID($or) || cell->get_bool_attribute(ID::keep))
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return false;
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SigSpec y = sigmap(cell->getPort(ID::Y));
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SigSpec a = sigmap(cell->getPort(ID::A));
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SigSpec b = sigmap(cell->getPort(ID::B));
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int width = GetSize(y);
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if (width == 0)
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return false;
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std::vector<SelectGroup> groups;
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for (int bit_idx = 0; bit_idx < width; bit_idx++)
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{
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BitContribs bit_contribs;
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if (!collect_bit_contribs(cell, bit_idx, bit_contribs))
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continue;
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bool found = false;
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for (auto &group : groups) {
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if (group.select == bit_contribs.select) {
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group.bits.push_back(bit_contribs);
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found = true;
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break;
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}
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}
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if (!found)
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groups.push_back({bit_contribs.select, {bit_contribs}});
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}
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pool<int> converted_bits;
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for (auto &group : groups)
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convert_group(cell, group, converted_bits);
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if (converted_bits.empty())
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return false;
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SigSpec keep_a, keep_b, keep_y;
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for (int bit_idx = 0; bit_idx < width; bit_idx++) {
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if (converted_bits.count(bit_idx))
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continue;
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keep_a.append(a[bit_idx]);
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keep_b.append(b[bit_idx]);
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keep_y.append(y[bit_idx]);
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}
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std::string src = cell->get_src_attribute();
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if (!keep_y.empty())
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module->addOr(NEW_ID2_SUFFIX("andor_pmux_keep_or"), keep_a, keep_b, keep_y, false, src);
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removed_cells.insert(cell);
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module->remove(cell);
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converted_count++;
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return true;
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}
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@ -448,7 +533,8 @@ struct OptAndOrPmuxWorker
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cells.push_back(cell);
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for (auto cell : cells)
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try_convert(cell);
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if (try_convert(cell))
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build_maps();
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}
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};
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@ -466,6 +552,7 @@ struct OptAndOrPmuxPass : public Pass {
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log("\n");
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log("into $pmux cells. It only rewrites terms whose select conditions are\n");
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log("equality comparisons against distinct constants of the same select signal.\n");
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log("Very small conversions are ignored to avoid replacing tiny boolean cones.\n");
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log("\n");
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}
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@ -0,0 +1,48 @@
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module mixed_vector_decode(
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input [2:0] sel0,
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input [2:0] sel1,
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input [3:0] a0,
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input [3:0] b0,
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input [3:0] c0,
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input [3:0] a1,
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input [3:0] b1,
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input [3:0] c1,
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output [3:0] y0,
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output [3:0] y1
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);
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assign {y1, y0} =
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({ {4{sel1 == 3'd1}}, {4{sel0 == 3'd1}} } & {a1, a0}) |
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({ {4{sel1 == 3'd2}}, {4{sel0 == 3'd2}} } & {b1, b0}) |
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({ {4{sel1 == 3'd3}}, {4{sel0 == 3'd3}} } & {c1, c0});
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endmodule
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module partial_vector_decode(
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input [2:0] sel0,
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input [2:0] sel1,
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input [3:0] a0,
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input [3:0] b0,
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input [3:0] c0,
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input [3:0] a1,
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input [3:0] b1,
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input [3:0] c1,
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input [3:0] passthru,
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output [3:0] y0,
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output [3:0] y1
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);
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wire [7:0] stage =
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({ {4{sel1 == 3'd1}}, {4{sel0 == 3'd1}} } & {a1, a0}) |
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({ {4{sel1 == 3'd2}}, {4{sel0 == 3'd2}} } & {b1, b0}) |
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({ {4{sel1 == 3'd3}}, {4{sel0 == 3'd3}} } & {c1, c0});
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assign y1 = stage[7:4];
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assign y0 = stage[3:0] | passthru;
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endmodule
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module tiny_decode(
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input [1:0] sel,
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input a,
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input b,
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output y
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);
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assign y = ((sel == 2'd1) & a) | ((sel == 2'd2) & b);
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endmodule
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@ -0,0 +1,38 @@
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read_verilog opt_andor_pmux.v
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hierarchy -top mixed_vector_decode
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proc
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design -save mixed_gold
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opt_andor_pmux
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select -assert-count 2 t:$pmux
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design -stash mixed_gate
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design -copy-from mixed_gold -as gold mixed_vector_decode
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design -copy-from mixed_gate -as gate mixed_vector_decode
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-inputs -show-outputs miter
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design -reset
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read_verilog opt_andor_pmux.v
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hierarchy -top partial_vector_decode
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proc
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design -save partial_gold
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opt_andor_pmux
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select -assert-count 2 t:$pmux
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design -stash partial_gate
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design -copy-from partial_gold -as gold partial_vector_decode
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design -copy-from partial_gate -as gate partial_vector_decode
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-inputs -show-outputs miter
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design -reset
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read_verilog opt_andor_pmux.v
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hierarchy -top tiny_decode
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proc
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opt_andor_pmux
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select -assert-count 0 t:$pmux
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