mirror of https://github.com/YosysHQ/yosys.git
opt_merge: newcelltypes
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@ -21,7 +21,7 @@
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#include "kernel/ffinit.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include "kernel/celltypes.h"
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#include "kernel/newcelltypes.h"
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#include "libs/sha1/sha1.h"
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#include "passes/opt/opt_merge_common.h"
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#include <stdlib.h>
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@ -36,6 +36,31 @@ USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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using OptMergeCommon::CellHasher;
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using MergeableTypes = StaticCellTypes::Categories::Category;
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// setup_internals + setup_internals_mem + setup_stdcells + setup_stdcells_mem,
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// minus a fixed set of cells we never want to merge. setup_internals_anyinit
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// is intentionally not included, so $anyinit stays excluded
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static constexpr MergeableTypes build_mergeable_types(bool nomux) {
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auto c = StaticCellTypes::categories.is_known;
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c.set_id(ID($anyinit), false);
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c.set_id(ID($tribuf), false);
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c.set_id(ID($_TBUF_), false);
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c.set_id(ID($anyseq), false);
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c.set_id(ID($anyconst), false);
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c.set_id(ID($allseq), false);
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c.set_id(ID($allconst), false);
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c.set_id(ID($connect), false);
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c.set_id(ID($input_port), false);
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if (nomux) {
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c.set_id(ID($mux), false);
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c.set_id(ID($pmux), false);
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}
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return c;
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}
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static constexpr MergeableTypes mergeable_with_mux = build_mergeable_types(false);
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static constexpr MergeableTypes mergeable_without_mux = build_mergeable_types(true);
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struct OptMergeIncWorker
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{
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@ -45,33 +70,15 @@ struct OptMergeIncWorker
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FfInitVals initvals;
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bool mode_share_all;
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CellTypes ct;
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const MergeableTypes &ct;
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int total_count;
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CellHasher hasher;
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OptMergeIncWorker(RTLIL::Design *design, RTLIL::Module *module, bool mode_nomux, bool mode_share_all, bool mode_keepdc) :
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design(design), module(module), mode_share_all(mode_share_all),
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OptMergeIncWorker(RTLIL::Design *design, RTLIL::Module *module, const MergeableTypes &ct, bool mode_share_all, bool mode_keepdc) :
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design(design), module(module), mode_share_all(mode_share_all), ct(ct),
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hasher(assign_map, initvals, /*apply_sigmap=*/false)
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{
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total_count = 0;
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ct.setup_internals();
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ct.setup_internals_mem();
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ct.setup_stdcells();
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ct.setup_stdcells_mem();
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if (mode_nomux) {
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ct.cell_types.erase(ID($mux));
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ct.cell_types.erase(ID($pmux));
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}
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ct.cell_types.erase(ID($tribuf));
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ct.cell_types.erase(ID($_TBUF_));
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ct.cell_types.erase(ID($anyseq));
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ct.cell_types.erase(ID($anyconst));
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ct.cell_types.erase(ID($allseq));
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ct.cell_types.erase(ID($allconst));
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ct.cell_types.erase(ID($connect));
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ct.cell_types.erase(ID($input_port));
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log("Finding identical cells in module `%s'.\n", module->name);
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assign_map.set(module);
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@ -162,7 +169,7 @@ struct OptMergeIncWorker
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continue;
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if (!cell->known())
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continue;
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if (!mode_share_all && !ct.cell_known(cell->type))
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if (!mode_share_all && !ct(cell->type))
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continue;
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cells.push_back(cell);
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@ -191,7 +198,7 @@ struct OptMergeIncWorker
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continue;
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if (!cell->known())
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continue;
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if (!mode_share_all && !ct.cell_known(cell->type))
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if (!mode_share_all && !ct(cell->type))
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continue;
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@ -418,9 +425,11 @@ struct OptMergeIncPass : public Pass {
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design->sigNormalize(true);
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const MergeableTypes &ct = mode_nomux ? mergeable_without_mux : mergeable_with_mux;
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int total_count = 0;
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for (auto module : design->selected_modules()) {
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OptMergeIncWorker worker(design, module, mode_nomux, mode_share_all, mode_keepdc);
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OptMergeIncWorker worker(design, module, ct, mode_share_all, mode_keepdc);
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total_count += worker.total_count;
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}
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