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Add Xilinx RAM64X1D and RAM128X1D simulation models

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This commit is contained in:
Clifford Wolf
2018-03-07 17:31:48 +01:00
parent 73c01dca65
commit 6991c132b5
4 changed files with 30 additions and 23 deletions
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techlibs/xilinx/synth_xilinx.cc
-2
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@@ -71,7 +71,6 @@ struct SynthXilinxPass : public Pass {
log(" read_verilog -lib +/xilinx/cells_sim.v\n");
log(" read_verilog -lib +/xilinx/cells_xtra.v\n");
log(" read_verilog -lib +/xilinx/brams_bb.v\n");
log(" read_verilog -lib +/xilinx/drams_bb.v\n");
log(" hierarchy -check -top <top>\n");
log("\n");
log(" flatten: (only if -flatten)\n");
@@ -168,7 +167,6 @@ struct SynthXilinxPass : public Pass {
Pass::call(design, "read_verilog -lib +/xilinx/cells_sim.v");
Pass::call(design, "read_verilog -lib +/xilinx/cells_xtra.v");
Pass::call(design, "read_verilog -lib +/xilinx/brams_bb.v");
Pass::call(design, "read_verilog -lib +/xilinx/drams_bb.v");
Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str()));
}