mirror of https://github.com/YosysHQ/yosys.git
sim: early-return from checkSignals in sim mode
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@ -1235,6 +1235,10 @@ struct SimInstance
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bool checkSignals()
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bool checkSignals()
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{
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{
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// No checks performed when using stimulus
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if (shared->sim_mode == SimulationMode::sim)
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return false;
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bool retVal = false;
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bool retVal = false;
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for(auto &item : fst_handles) {
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for(auto &item : fst_handles) {
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if (item.second==0) continue; // Ignore signals not found
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if (item.second==0) continue; // Ignore signals not found
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@ -1244,9 +1248,7 @@ struct SimInstance
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log_warning("Signal '%s.%s' size is different in gold and gate.\n", scope, log_id(item.first));
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log_warning("Signal '%s.%s' size is different in gold and gate.\n", scope, log_id(item.first));
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continue;
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continue;
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}
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}
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if (shared->sim_mode == SimulationMode::sim) {
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if (shared->sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X
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// No checks performed when using stimulus
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} else if (shared->sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X
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for(int i=0;i<fst_val.size();i++) {
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for(int i=0;i<fst_val.size();i++) {
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if (fst_val[i]!=State::Sx && fst_val[i]!=sim_val[i]) {
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if (fst_val[i]!=State::Sx && fst_val[i]!=sim_val[i]) {
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log_warning("Signal '%s.%s' in file %s in simulation %s\n", scope, log_id(item.first), log_signal(fst_val), log_signal(sim_val));
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log_warning("Signal '%s.%s' in file %s in simulation %s\n", scope, log_id(item.first), log_signal(fst_val), log_signal(sim_val));
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