mirror of https://github.com/YosysHQ/yosys.git
tests: fix fsm.ys
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@ -5,7 +5,7 @@ flatten
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equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5
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equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5
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miter -equiv -make_assert -flatten gold gate miter
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miter -equiv -make_assert -flatten gold gate miter
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techmap -map +/dff2ff.v
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formalff -clk2ff
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sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
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sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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@ -5,6 +5,7 @@ flatten
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equiv_opt -run :prove -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f
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equiv_opt -run :prove -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f
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async2sync
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async2sync
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formalff -clk2ff
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miter -equiv -make_assert -flatten gold gate miter
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miter -equiv -make_assert -flatten gold gate miter
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sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
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sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
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