smt2 backend produces verilog testbench which errors out with Verilator; genclock is defined twice. This patch removes the redefinition of genclock.

2025-05-14 10:05:07 -07:00 · 2025-05-14 10:05:07 -07:00 · 62b29b0b75
parent e3ae7b1400
commit 62b29b0b75
1 changed files with 0 additions and 1 deletions
--- a/backends/smt2/smtbmc.py
+++ b/backends/smt2/smtbmc.py
@ -1161,7 +1161,6 @@ def write_vlogtb_trace(steps, index):
        print("  initial genclock = 1;", file=f)
        print("`endif", file=f)

-        print("  reg genclock = 1;", file=f)
        print("  reg [31:0] cycle = 0;", file=f)

        primary_inputs = list()