verilog: test cases that look like SVA labels #862

tests/verilog/sva-in-case-expr.ys

@@ -0,0 +1,10 @@
+read_verilog -sv <<EOT
+module test(input wire A);
+  localparam TEST = 1;
+  always_comb begin
+    case (A)
+      TEST: assert(1);
+    endcase
+  end
+endmodule
+EOT