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gowin: remove lib_whitebox from latch sim cells 

Latches are sequential elements and don't need lib_whitebox.
This commit is contained in:
Justin Zaun 2026-03-02 16:22:33 -10:00
parent 8e97f34d31
commit 5cc76ceabb
1 changed files with 0 additions and 12 deletions
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12
techlibs/gowin/cells_sim.v
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@ -543,7 +543,6 @@ endmodule // DFFNCE (negative clock edge; asynchronous clear; clock enable)
// Latch sim cells
// Gate signal uses CLK port name to match the physical DFF BEL pin
(* lib_whitebox *)
module DL (output reg Q, input D, CLK);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
@ -551,7 +550,6 @@ module DL (output reg Q, input D, CLK);
if (CLK) Q <= D;
endmodule
(* lib_whitebox *)
module DLN (output reg Q, input D, CLK);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
@ -559,7 +557,6 @@ module DLN (output reg Q, input D, CLK);
if (!CLK) Q <= D;
endmodule
(* lib_whitebox *)
module DLE (output reg Q, input D, CLK, CE);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
@ -567,7 +564,6 @@ module DLE (output reg Q, input D, CLK, CE);
if (CLK && CE) Q <= D;
endmodule
(* lib_whitebox *)
module DLNE (output reg Q, input D, CLK, CE);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
@ -575,7 +571,6 @@ module DLNE (output reg Q, input D, CLK, CE);
if (!CLK && CE) Q <= D;
endmodule
(* lib_whitebox *)
module DLC (output reg Q, input D, CLK, CLEAR);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
@ -584,7 +579,6 @@ module DLC (output reg Q, input D, CLK, CLEAR);
else if (CLK) Q <= D;
endmodule
(* lib_whitebox *)
module DLCE (output reg Q, input D, CLK, CE, CLEAR);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
@ -593,7 +587,6 @@ module DLCE (output reg Q, input D, CLK, CE, CLEAR);
else if (CLK && CE) Q <= D;
endmodule
(* lib_whitebox *)
module DLNC (output reg Q, input D, CLK, CLEAR);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
@ -602,7 +595,6 @@ module DLNC (output reg Q, input D, CLK, CLEAR);
else if (!CLK) Q <= D;
endmodule
(* lib_whitebox *)
module DLNCE (output reg Q, input D, CLK, CE, CLEAR);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
@ -611,7 +603,6 @@ module DLNCE (output reg Q, input D, CLK, CE, CLEAR);
else if (!CLK && CE) Q <= D;
endmodule
(* lib_whitebox *)
module DLP (output reg Q, input D, CLK, PRESET);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
@ -620,7 +611,6 @@ module DLP (output reg Q, input D, CLK, PRESET);
else if (CLK) Q <= D;
endmodule
(* lib_whitebox *)
module DLPE (output reg Q, input D, CLK, CE, PRESET);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
@ -629,7 +619,6 @@ module DLPE (output reg Q, input D, CLK, CE, PRESET);
else if (CLK && CE) Q <= D;
endmodule
(* lib_whitebox *)
module DLNP (output reg Q, input D, CLK, PRESET);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
@ -638,7 +627,6 @@ module DLNP (output reg Q, input D, CLK, PRESET);
else if (!CLK) Q <= D;
endmodule
(* lib_whitebox *)
module DLNPE (output reg Q, input D, CLK, CE, PRESET);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;