mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #5555 from rocallahan/defer-redirects
Defer redirecting cell outputs when merging cells in `opt_merge` untill after we've done a full pass over the cells.
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commit
5c630a366d
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@ -289,6 +289,7 @@ struct OptMergeWorker
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CellPtrHash,
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CellPtrHash,
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CellPtrEqual> known_cells (0, CellPtrHash(*this), CellPtrEqual(*this));
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CellPtrEqual> known_cells (0, CellPtrHash(*this), CellPtrEqual(*this));
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std::vector<RTLIL::SigSig> redirects;
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for (auto cell : cells)
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for (auto cell : cells)
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{
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{
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auto [cell_in_map, inserted] = known_cells.insert(cell);
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auto [cell_in_map, inserted] = known_cells.insert(cell);
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@ -310,12 +311,7 @@ struct OptMergeWorker
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RTLIL::SigSpec other_sig = other_cell->getPort(it.first);
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RTLIL::SigSpec other_sig = other_cell->getPort(it.first);
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log_debug(" Redirecting output %s: %s = %s\n", it.first,
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log_debug(" Redirecting output %s: %s = %s\n", it.first,
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log_signal(it.second), log_signal(other_sig));
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log_signal(it.second), log_signal(other_sig));
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Const init = initvals(other_sig);
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redirects.push_back(RTLIL::SigSig(it.second, std::move(other_sig)));
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initvals.remove_init(it.second);
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initvals.remove_init(other_sig);
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module->connect(RTLIL::SigSig(it.second, other_sig));
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assign_map.add(it.second, other_sig);
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initvals.set_init(other_sig, init);
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}
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}
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}
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}
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log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type, cell->name, module->name);
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log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type, cell->name, module->name);
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@ -323,6 +319,14 @@ struct OptMergeWorker
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total_count++;
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total_count++;
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}
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}
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}
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}
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for (const RTLIL::SigSig &redirect : redirects) {
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module->connect(redirect);
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Const init = initvals(redirect.second);
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initvals.remove_init(redirect.first);
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initvals.remove_init(redirect.second);
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assign_map.add(redirect.first, redirect.second);
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initvals.set_init(redirect.second, init);
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}
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}
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}
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log_suppressed();
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log_suppressed();
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