intel_alm: direct LUTRAM cell instantiation

By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.

While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.

techlibs/intel_alm/common/bram_m10k_map.v

@@ -28,4 +28,4 @@ altsyncram #(
     .clock1(CLK1)
 );
 
-endmodule
+endmodule