Add test for bug 3462

tests/various/bug3462.ys

@@ -0,0 +1,12 @@
+read_verilog <<EOT
+module top();
+    wire array[0:0];
+    wire out;
+    sub #(.d(1)) inst(
+        .in(array[0]),
+        .out(out)
+    );
+endmodule
+EOT
+
+hierarchy -top top -libdir .

tests/various/sub.v

@@ -0,0 +1,3 @@
+module sub #(parameter d=1) (input in, output out);
+    assign out = in;
+endmodule