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Zero out ports

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This commit is contained in:
Eddie Hung
2019-09-26 13:40:38 -07:00
parent af59856ba1
commit 58f31096ab
1 changed files with 2 additions and 2 deletions
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passes/pmgen/xilinx_dsp_cascade.pmg
+2 -2
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@@ -67,7 +67,7 @@ finally
Wire *cascade = module->addWire(NEW_ID, 30); Wire *cascade = module->addWire(NEW_ID, 30);
dsp_pcin->setPort(ID(ACIN), cascade); dsp_pcin->setPort(ID(ACIN), cascade);
dsp->setPort(ID(ACOUT), cascade); dsp->setPort(ID(ACOUT), cascade);
dsp_pcin->unsetPort(ID(A)); dsp_pcin->setPort(ID(A), Const(0, 30));
add_siguser(cascade, dsp_pcin); add_siguser(cascade, dsp_pcin);
add_siguser(cascade, dsp); add_siguser(cascade, dsp);
@@ -80,7 +80,7 @@ finally
Wire *cascade = module->addWire(NEW_ID, 18); Wire *cascade = module->addWire(NEW_ID, 18);
dsp_pcin->setPort(ID(BCIN), cascade); dsp_pcin->setPort(ID(BCIN), cascade);
dsp->setPort(ID(BCOUT), cascade); dsp->setPort(ID(BCOUT), cascade);
dsp_pcin->unsetPort(ID(B)); dsp_pcin->setPort(ID(B), Const(0, 18));
add_siguser(cascade, dsp_pcin); add_siguser(cascade, dsp_pcin);
add_siguser(cascade, dsp); add_siguser(cascade, dsp);