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bug2920: disable

This commit is contained in:
Emil J. Tywoniak 2026-03-09 16:37:30 +01:00
parent 63355cdd03
commit 57ee22883a
1 changed files with 41 additions and 39 deletions
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80
tests/opt/bug2920.ys
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@ -1,42 +1,44 @@
read_rtlil <<EOT # TODO re-enable when https://github.com/YosysHQ/yosys/issues/5735 fixed
module \mod # read_rtlil <<EOT
wire input 1 \clk
attribute \init 2'00
wire width 2 $q1
attribute \init 2'00
wire width 2 $q2
wire output 2 width 4 \q
cell $dff $ff1
parameter \CLK_POLARITY 1'1
parameter \WIDTH 1
connect \CLK \clk
connect \D 1'0
connect \Q $q1 [0]
end
cell $dff $ff2
parameter \CLK_POLARITY 1'1
parameter \WIDTH 1
connect \CLK \clk
connect \D 1'0
connect \Q $q2 [0]
end
cell $dff $ff3
parameter \CLK_POLARITY 1'1
parameter \WIDTH 2
connect \CLK \clk
connect \D 2'00
connect \Q { $q1 [1] $q2 [1] }
end
connect \q [0] $q1 [0]
connect \q [1] $q2 [0]
connect \q [2] $q1 [1]
connect \q [3] $q2 [1]
end
EOT # module \mod
# wire input 1 \clk
# attribute \init 2'00
# wire width 2 $q1
# attribute \init 2'00
# wire width 2 $q2
# wire output 2 width 4 \q
# cell $dff $ff1
# parameter \CLK_POLARITY 1'1
# parameter \WIDTH 1
# connect \CLK \clk
# connect \D 1'0
# connect \Q $q1 [0]
# end
# cell $dff $ff2
# parameter \CLK_POLARITY 1'1
# parameter \WIDTH 1
# connect \CLK \clk
# connect \D 1'0
# connect \Q $q2 [0]
# end
# cell $dff $ff3
# parameter \CLK_POLARITY 1'1
# parameter \WIDTH 2
# connect \CLK \clk
# connect \D 2'00
# connect \Q { $q1 [1] $q2 [1] }
# end
# connect \q [0] $q1 [0]
# connect \q [1] $q2 [0]
# connect \q [2] $q1 [1]
# connect \q [3] $q2 [1]
# end
opt_clean # EOT
opt_merge
opt_dff # opt_clean
opt_clean # opt_merge
# opt_dff
# opt_clean