Add more correctness tests.

tests/techmap/abc_new_box.ys

@@ -0,0 +1,18 @@
+read_verilog -icells -specify <<EOT
+(* abc9_box, blackbox *)
+module box1(input i, output o);
+specify
+	(i => o) = 1;
+endspecify
+endmodule
+
+module top(input a, input b, output o);
+	wire z;
+	$_AND_ gate(.A(a), .B(b), .Y(o));
+	box1 u_box(.i(a), .o(z));
+endmodule
+EOT
+
+hierarchy -check -top top
+abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
+select -assert-min 1 t:*

tests/techmap/abc_new_equiv_opt.ys

@@ -0,0 +1,14 @@
+read_verilog <<EOT
+module top(input a, input b, input c, output y, output z);
+	assign y = ~(a & b);
+	assign z = ~(a | c);
+endmodule
+EOT
+hierarchy -check -top top
+proc; opt -fast
+abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
+
+select -assert-min 1 t:NAND
+select -assert-min 1 t:NOR
+select -assert-min 1 t:NAND t:NOT t:NOR t:BUF %u
+select -assert-none t:$_AND_ t:$_OR_ t:$_NAND_ t:$_NOR_ %u

tests/techmap/abc_new_keep.ys

@@ -0,0 +1,12 @@
+read_verilog <<EOT
+module top(input a, input b, output o);
+	(* keep *) wire w = a & b;
+	assign o = ~w;
+endmodule
+EOT
+hierarchy -check -top top
+proc; opt -fast; techmap
+
+abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
+select -assert-none t:$_AND_
+select -assert-min 1 t:NAND t:NOT t:NOR t:BUF %u

tests/techmap/abc_new_temp_sanitization.ys

@@ -0,0 +1,11 @@
+read_verilog <<EOT
+module top(input a, input b, output y);
+	assign y = a | b;
+endmodule
+EOT
+hierarchy -check -top top
+proc; opt -fast
+
+logger -expect log " /tmp/" 2
+abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
+