luke/yosys
1
0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-28 17:14:11 +02:00
Code Issues Packages Projects Releases Wiki Activity

DSP48E1 model: test CE inputs

Browse Source 
Signed-off-by: David Shah <[email protected]>
This commit is contained in:
David Shah
2019-08-08 11:32:43 +01:00
parent d60b3c0dc8
commit 57aeb4cc01
2 changed files with 17 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files
techlibs/xilinx/tests/test_dsp_model.v
+9 -2
View File
@@ -134,7 +134,7 @@ module testbench;
end
{RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP} = 0;
repeat (5000) begin
repeat (10000) begin
clkcycle;
config_valid = 0;
while (!config_valid) begin
@@ -146,6 +146,13 @@ module testbench;
D = $urandom;
PCIN = {$urandom, $urandom};
{CEA1, CEA2, CEAD, CEALUMODE, CEB1, CEB2, CEC, CECARRYIN, CECTRL} = $urandom | $urandom | $urandom;
{CED, CEINMODE, CEM, CEP} = $urandom | $urandom | $urandom | $urandom;
// Otherwise we can accidentally create illegal configs
CEINMODE = CECTRL;
CEALUMODE = CECTRL;
{RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP} = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom;
{ALUMODE, INMODE} = $urandom;
CARRYINSEL = $urandom & $urandom & $urandom;
@@ -162,7 +169,7 @@ module testbench;
if (CARRYINSEL == 3'b101) OPMODE = 7'b0011010;
if (CARRYINSEL == 3'b110) OPMODE = 7'b0010101;
if (CARRYINSEL == 3'b111) OPMODE = 7'b0100011;
drc;
end
end