mirror of https://github.com/YosysHQ/yosys.git
fix value conversion bug
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parent
448ab2a4e7
commit
550d48c417
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@ -108,8 +108,16 @@ struct RegRenameInstance {
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size_t last_open = cellName.rfind('[');
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size_t last_close = cellName.rfind(']');
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if (last_open != std::string::npos && last_close != std::string::npos && last_close > last_open) {
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// Check that bracket content is just a single bit index
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std::string inner = cellName.substr(last_open + 1, last_close - last_open - 1);
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if (!inner.empty() && inner.find_first_not_of("0123456789") == std::string::npos) {
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wireName = cellName.substr(0, last_open);
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bitIndex = std::stoi(cellName.substr(last_open + 1, last_close - last_open - 1));
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bitIndex = std::stoi(inner);
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} else {
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wireName = cellName;
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bitIndex = 0;
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}
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} else {
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wireName = cellName;
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bitIndex = 0;
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@ -301,10 +309,17 @@ struct RegRenamePass : public Pass {
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std::string signal_bits = "";
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// Use the bracket notation to extract the bit range and construct true reg name.
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size_t bit_pos = signal_name.rfind('[');
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if (bit_pos != std::string::npos) {
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signal_bits = signal_name.substr(bit_pos);
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signal_name.erase(bit_pos);
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if (!signal_name.empty() && signal_name.back() == ']') {
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size_t open = signal_name.rfind('[');
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if (open != std::string::npos) {
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std::string inner = signal_name.substr(open + 1,
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signal_name.size() - open - 2);
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// Check for alphabetical characters since they can be contained in brackets in a wire name.
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if (!inner.empty() && inner.find_first_not_of("0123456789:") == std::string::npos) {
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signal_bits = signal_name.substr(open);
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signal_name.erase(open);
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}
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}
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}
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// Extract the LSB and MSB indices if present.
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