mirror of https://github.com/YosysHQ/yosys.git
rtlil_bufnorm: fix setup_driven_wires constant handling on unknown port direction
This commit is contained in:
parent
a52b8d2f91
commit
54ef1275bd
|
|
@ -135,7 +135,8 @@ struct RTLIL::SigNormIndex
|
|||
wire->driverPort_ = port;
|
||||
|
||||
xlog("therefore connect port %s %s %s\n", port, log_signal(sig), wire->name);
|
||||
module->connect(sig, wire);
|
||||
// This orientation bias is potentially dangerous elsewhere
|
||||
module->connect(wire, sig);
|
||||
sig = wire;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue