mirror of https://github.com/YosysHQ/yosys.git
Reenable Verific opt and comment out clock enable muxing
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6993fc2540
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54653fc82c
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@ -3129,8 +3129,8 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
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if (verific_opt) {
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log(" Optimizing netlist for %s.\n", it->first.c_str());
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log(" Inferring clock enable muxes for %s.\n", it->first.c_str());
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nl->InferClockEnableMux();
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// log(" Inferring clock enable muxes for %s.\n", it->first.c_str());
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// nl->InferClockEnableMux();
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log(" Running post-elaboration for %s.\n", it->first.c_str());
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nl->PostElaborationProcess();
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@ -3613,10 +3613,6 @@ struct VerificPass : public Pass {
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verific_verbose = 0;
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verific_sva_fsm_limit = 16;
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// SILIMATE: added flags
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verific_opt = false;
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verific_no_split_complex_ports = false;
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const char *release_str = Message::ReleaseString();
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time_t release_time = Message::ReleaseDate();
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char *release_tmstr = ctime(&release_time);
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