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techmap inside map_cells stage

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This commit is contained in:
Eddie Hung
2019-04-05 12:55:52 -07:00
parent 7b7ddbdba7
commit 544843da71
2 changed files with 1 additions and 2 deletions
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techlibs/xilinx/synth_xilinx.cc
+1 -1
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@@ -283,7 +283,7 @@ struct SynthXilinxPass : public Pass
if (check_label(active, run_from, run_to, "map_cells"))
{
Pass::call(design, "techmap -map +/xilinx/cells_map.v");
Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/cells_map.v");
Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
Pass::call(design, "clean");