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Merge 3d6d9c5d4f into b864f70e52

This commit is contained in:
Abhinav Kumar Puthran 2026-05-05 09:43:39 +02:00 committed by GitHub
parent b864f70e52 3d6d9c5d4f
commit 53c999797a
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GPG Key ID: B5690EEEBB952194
2 changed files with 66 additions and 0 deletions
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10
passes/sat/async2sync.cc
View File

@ -153,7 +153,10 @@ struct Async2syncPass : public Pass {
initvals.remove_init(ff.sig_q); initvals.remove_init(ff.sig_q);
Wire *new_d = module->addWire(NEW_ID, ff.width); Wire *new_d = module->addWire(NEW_ID, ff.width);
new_d->set_src_attribute(cell->get_src_attribute());
Wire *new_q = module->addWire(NEW_ID, ff.width); Wire *new_q = module->addWire(NEW_ID, ff.width);
new_q->set_src_attribute(cell->get_src_attribute());
SigSpec sig_set = ff.sig_set; SigSpec sig_set = ff.sig_set;
SigSpec sig_clr = ff.sig_clr; SigSpec sig_clr = ff.sig_clr;
@ -218,7 +221,10 @@ struct Async2syncPass : public Pass {
initvals.remove_init(ff.sig_q); initvals.remove_init(ff.sig_q);
Wire *new_d = module->addWire(NEW_ID, ff.width); Wire *new_d = module->addWire(NEW_ID, ff.width);
new_d->set_src_attribute(cell->get_src_attribute());
Wire *new_q = module->addWire(NEW_ID, ff.width); Wire *new_q = module->addWire(NEW_ID, ff.width);
new_q->set_src_attribute(cell->get_src_attribute());
if (ff.pol_aload) { if (ff.pol_aload) {
if (!ff.is_fine) { if (!ff.is_fine) {
@ -251,6 +257,7 @@ struct Async2syncPass : public Pass {
initvals.remove_init(ff.sig_q); initvals.remove_init(ff.sig_q);
Wire *new_q = module->addWire(NEW_ID, ff.width); Wire *new_q = module->addWire(NEW_ID, ff.width);
new_q->set_src_attribute(cell->get_src_attribute());
if (ff.pol_arst) { if (ff.pol_arst) {
if (!ff.is_fine) if (!ff.is_fine)
@ -285,10 +292,13 @@ struct Async2syncPass : public Pass {
initvals.remove_init(ff.sig_q); initvals.remove_init(ff.sig_q);
Wire *new_q = module->addWire(NEW_ID, ff.width); Wire *new_q = module->addWire(NEW_ID, ff.width);
new_q->set_src_attribute(cell->get_src_attribute());
Wire *new_d; Wire *new_d;
if (ff.has_aload) { if (ff.has_aload) {
new_d = module->addWire(NEW_ID, ff.width); new_d = module->addWire(NEW_ID, ff.width);
new_d->set_src_attribute(cell->get_src_attribute());
if (ff.pol_aload) { if (ff.pol_aload) {
if (!ff.is_fine) if (!ff.is_fine)
module->addMux(NEW_ID, new_q, ff.sig_ad, ff.sig_aload, new_d); module->addMux(NEW_ID, new_q, ff.sig_ad, ff.sig_aload, new_d);

56
tests/sat/async2sync.ys Normal file
View File

@ -0,0 +1,56 @@
# has_arst path
read_verilog << EOT
module top(input clk, arst, d, output reg q);
always @(posedge clk or posedge arst)
if (arst) q <= 0;
else q <= d;
endmodule
EOT
proc
async2sync
select -assert-count 1 w:$auto$async2sync* a:src=* %i
design -reset
# has_sr path
read_verilog << EOT
module sr(input clk, set, clr, d, output reg q);
always @(posedge clk or posedge set or posedge clr)
if (clr) q <= 0;
else if (set) q <= 1;
else q <= d;
endmodule
EOT
proc
async2sync
select -assert-count 2 w:$auto$async2sync* a:src=* %i
design -reset
# has_aload path
read_verilog << EOT
module aload(input clk, aload, d, ad, output reg q);
always @(posedge clk or posedge aload)
if (aload) q <= ad;
else q <= d;
endmodule
EOT
proc
async2sync
select -assert-count 2 w:$auto$async2sync* a:src=* %i
design -reset
# latch path
read_verilog << EOT
module latch(input en, arst, d, output reg q);
always @(*)
if (arst) q <= 0;
else if (en) q <= d;
endmodule
EOT
proc
async2sync
# latch with async reset path creates 2 wires (new_q + new_d from has_arst handling)
select -assert-count 2 w:$auto$async2sync* a:src=* %i
design -reset
# a latch where has_aload is false (no async load) cannot be tested here
# because proc optimizes it away into muxes before async2sync runs,
# leaving no latch cell for async2sync to process.