mirror of
https://github.com/YosysHQ/yosys.git
synced 2026-08-22 14:17:27 +02:00
Added $global_clock verilog syntax support for creating $ff cells
This commit is contained in:
+2
-1
@@ -42,7 +42,8 @@ namespace RTLIL
|
||||
STn = 3, // edge sensitive: negedge
|
||||
STe = 4, // edge sensitive: both edges
|
||||
STa = 5, // always active
|
||||
STi = 6 // init
|
||||
STg = 6, // global clock
|
||||
STi = 7 // init
|
||||
};
|
||||
|
||||
enum ConstFlags : unsigned char {
|
||||
|
||||
Reference in New Issue
Block a user