mirror of https://github.com/YosysHQ/yosys.git
Add muxpacker draft
This commit is contained in:
Akash Levy
parent
d4119e1ad3
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2017 Robert Ou <rqou@robertou.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include <deque>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct MuxpackerPass : public Pass
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{
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MuxpackerPass() : Pass("muxpacker", "convert $mux/$pmux trees into $pmux cells") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" muxpacker [options] [selection]\n");
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log("\n");
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log("convert $mux/$pmux trees into $pmux cells\n");
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log("\n");
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log("This command finds chains of $mux and $pmux cells and replaces them\n");
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log("with them with $pmux cells.\n");
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log("\n");
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log(" -allow-off-chain\n");
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log(" Allows matching of cells that have loads outside the chain. These cells\n");
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log(" will be replicated and folded into the $reduce_* cell, but the original\n");
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log(" cell will remain, driving its original loads.\n");
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log("\n");
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log(" -assume-excl\n");
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log(" Assume that $mux select signals are exclusive. Will result in logical\n");
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log(" inequivalence if this assumption is incorrect.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing MUXPACKER pass (convert $mux/$pmux trees into $pmux cells).\n");
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log_push();
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size_t argidx;
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bool allow_off_chain = false, assume_excl = false;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-allow-off-chain")
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{
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allow_off_chain = true;
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continue;
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}
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if (args[argidx] == "-assume-excl")
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{
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assume_excl = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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SigMap sigmap(module);
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// Index all of the nets in the module
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dict<SigBit, Cell*> sig_to_driver;
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dict<SigBit, pool<Cell*>> sig_to_sink;
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for (auto cell : module->selected_cells())
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{
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for (auto &conn : cell->connections())
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{
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if (cell->output(conn.first))
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for (auto bit : sigmap(conn.second))
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sig_to_driver[bit] = cell;
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if (cell->input(conn.first))
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{
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for (auto bit : sigmap(conn.second))
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{
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if (sig_to_sink.count(bit) == 0)
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sig_to_sink[bit] = pool<Cell*>();
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sig_to_sink[bit].insert(cell);
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}
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}
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}
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}
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// Need to check if any wires connect to module ports
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pool<SigBit> port_sigs;
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for (auto wire : module->selected_wires())
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if (wire->port_input || wire->port_output)
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for (auto bit : sigmap(wire))
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port_sigs.insert(bit);
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// Actual logic starts here
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pool<Cell*> consumed_cells;
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for (auto cell : module->selected_cells())
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{
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// If we already consumed this cell, skip it
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if (consumed_cells.count(cell))
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continue;
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// If this cell is not a mux or pmux, skip it
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if (!cell->type.in(ID($mux), ID($pmux)))
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continue;
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// Work on the cell
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log_debug("Working on cell %s...\n", cell->name.c_str());
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/////////////////////////////////////////////////////////
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// PASS 1: determine the sinks using forward traversal //
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/////////////////////////////////////////////////////////
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// If looking for a single chain, follow linearly to the sink
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pool<Cell*> sinks;
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if (!allow_off_chain)
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{
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Cell* head_cell = cell;
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Cell* x = cell;
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while (true)
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{
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if (!x->type.in(ID($mux), ID($pmux)))
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break;
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head_cell = x;
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auto y = sigmap(x->getPort(ID::Y));
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log_assert(y.size() == 1);
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// Should only continue if there is one fanout back into a cell (not to a port)
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if (sig_to_sink[y].size() != 1 || port_sigs.count(y))
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break;
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// Traverse forward
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x = *sig_to_sink[y].begin();
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}
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sinks.insert(head_cell);
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}
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// If off-chain loads are allowed, do a wider traversal to find longest chain
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else
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{
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// Forward BFS, follow all chains until they hit a cell of a different type
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// Pick the longest one
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auto y = sigmap(cell->getPort(ID::Y));
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pool<Cell*> current_loads = sig_to_sink[y];
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pool<Cell*> next_loads;
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while (!current_loads.empty())
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{
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// Find each sink and see what they are
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for (auto x : current_loads)
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{
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// Not one of our gates? Don't follow any further
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// (but add the originating cell to the list of sinks)
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if (!x->type.in(ID($mux), ID($pmux)))
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{
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sinks.insert(cell);
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continue;
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}
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auto xy = sigmap(x->getPort(ID::Y));
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// If this signal drives a port, add it to the sinks
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// (even though it may not be the end of a chain)
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if (port_sigs.count(xy) && !consumed_cells.count(x))
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sinks.insert(x);
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// It's a match, search everything out from it
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auto& next = sig_to_sink[xy];
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for(auto z : next)
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next_loads.insert(z);
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}
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// If we couldn't find any downstream loads, stop
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// Create a reduction for each of the max-length chains we found
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if (next_loads.empty())
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{
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for(auto s : current_loads)
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{
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//Not one of our gates? Don't follow any further
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if (!x->type.in(ID($mux), ID($pmux)))
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continue;
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sinks.insert(s);
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}
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break;
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}
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// Otherwise, continue down the chain
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current_loads = next_loads;
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next_loads.clear();
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}
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}
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// We have our list, go act on it
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for(auto head_cell : sinks)
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{
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log_debug(" Head cell is %s\n", head_cell->name.c_str());
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// Avoid duplication if we already were covered
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if(consumed_cells.count(head_cell))
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continue;
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dict<SigBit, int> sources;
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dict<SigBit, int> sels;
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int inner_cells = 0;
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std::deque<std::pair<Cell*, SigBit>> bfs_queue = {{head_cell, State::S1}};
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while (bfs_queue.size())
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{
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auto bfs_item = bfs_queue.front();
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bfs_queue.pop_front();
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Cell* x = bfs_item.first;
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SigBit excl = bfs_item.second;
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for (auto port: {ID::B, ID::A}) {
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auto bit = sigmap(x->getPort(port)[0]);
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bool sink_single = sig_to_sink[bit].size() == 1 && !port_sigs.count(bit);
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Cell* drv = sig_to_driver[bit];
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bool drv_ok = drv && IsRightType(drv, gt);
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SigBit s_port;
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SigBit sel_sig;
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if (gt == GateType::Mux) {
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s_port = sigmap(x->getPort(ID::S)[0]);
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if (port == ID::A)
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sel_sig = module->Not(NEW_ID2_SUFFIX("not"), s_port, false, x->get_src_attribute());
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else
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sel_sig = module->Buf(NEW_ID2_SUFFIX("buf"), s_port, false, x->get_src_attribute());
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}
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if (drv_ok && (allow_off_chain || sink_single)) {
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inner_cells++;
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if (gt == GateType::Mux && !assume_excl) { // if not assuming exclusivity, add to excl signal
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SigBit sel_sig_inv = (port == ID::A) ? module->Not(NEW_ID2_SUFFIX("not"), s_port, false, x->get_src_attribute())[0] : s_port;
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bfs_queue.push_back({drv, module->And(NEW_ID2_SUFFIX("excl_and"), sel_sig_inv, excl, false, x->get_src_attribute())});
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} else { // otherwise, just use the drv signal and don't worry about exclusivity
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bfs_queue.push_back({drv, excl});
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}
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} else {
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sources[module->Buf(NEW_ID2_SUFFIX("buf"), bit, false, x->get_src_attribute())]++;
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if (gt == GateType::Mux) {
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if (assume_excl) // if assuming exclusivity, just use select signal
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sels[sel_sig]++;
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else // enforce exclusivity by ANDing with excl signal
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sels[module->And(NEW_ID2_SUFFIX("selex_and"), sel_sig, excl)]++;
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}
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}
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}
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}
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if (inner_cells)
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{
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// Worth it to create reduce cell
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log_debug("Creating reduce_* cell for %s (%s) in %s\n", head_cell->name.c_str(), head_cell->type.c_str(), module->name.c_str());
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SigBit output = sigmap(head_cell->getPort(ID::Y)[0]);
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SigSpec input, sel;
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for (auto it : sources) {
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bool cond;
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if (head_cell->type == ID($_XOR_) || head_cell->type == ID($xor) || head_cell->type == ID($_XNOR_) || head_cell->type == ID($xnor))
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cond = it.second & 1;
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else
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cond = it.second != 0;
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if (cond || head_cell->hasPort(ID::S))
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input.append(it.first);
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}
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if (head_cell->hasPort(ID::S)) {
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for (auto it : sels)
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sel.append(it.first);
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input.reverse();
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sel.reverse();
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}
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if (head_cell->type == ID($_AND_) || head_cell->type == ID($and)) {
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module->addReduceAnd(NEW_ID2_SUFFIX("reduce_and"), input, output, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
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} else if (head_cell->type == ID($_OR_) || head_cell->type == ID($or)) {
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module->addReduceOr(NEW_ID2_SUFFIX("reduce_or"), input, output, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
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} else if (head_cell->type == ID($_XOR_) || head_cell->type == ID($xor)) {
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module->addReduceXor(NEW_ID2_SUFFIX("reduce_xor"), input, output, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
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} else if (head_cell->type == ID($_XNOR_) || head_cell->type == ID($xnor)) {
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module->addReduceXnor(NEW_ID2_SUFFIX("reduce_xnor"), input, output, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
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} else if (head_cell->type == ID($_MUX_) || head_cell->type == ID($mux)) {
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module->addPmux(NEW_ID2_SUFFIX("pmux"), State::Sx, input, sel, output, cell->get_src_attribute()); // SILIMATE: Improve the naming
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} else {
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log_assert(false);
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}
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consumed_cells.insert(head_cell);
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}
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}
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}
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// Remove all of the head cells, since we supplant them.
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// Do not remove the upstream cells since some might still be in use ("clean" will get rid of unused ones)
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for (auto cell : consumed_cells)
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module->remove(cell);
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}
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log_pop();
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}
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} MuxpackerPass;
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PRIVATE_NAMESPACE_END
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