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FfData: some refactoring.

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- FfData now keeps track of the module and underlying cell, if any (so
  calling emit on FfData created from a cell will replace the existing cell)
- FfData implementation is split off to its own .cc file for faster
  compilation
- the "flip FF data sense by inserting inverters in front and after"
  functionality that zinit uses is moved onto FfData class and beefed up
  to have dffsr support, to support more use cases
This commit is contained in:
Marcelina Kościelnicka
2021-10-07 04:24:06 +02:00
parent 356ec7bb39
commit 4e70c30775
14 changed files with 663 additions and 549 deletions
Download Patch File Download Diff File Expand all files Collapse all files
passes/techmap/dffunmap.cc
+4 -5
View File
@@ -86,19 +86,18 @@ struct DffunmapPass : public Pass {
if (ce_only) {
if (!ff.has_ce)
continue;
ff.unmap_ce(mod);
ff.unmap_ce();
} else if (srst_only) {
if (!ff.has_srst)
continue;
ff.unmap_srst(mod);
ff.unmap_srst();
} else {
if (!ff.has_ce && !ff.has_srst)
continue;
ff.unmap_ce_srst(mod);
ff.unmap_ce_srst();
}
mod->remove(cell);
ff.emit(mod, name);
ff.emit();
}
}
}
passes/techmap/simplemap.cc
+2 -2
View File
@@ -368,13 +368,13 @@ void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell)
module->connect(RTLIL::SigSig(sig_y, sig_ab));
}
void simplemap_ff(RTLIL::Module *module, RTLIL::Cell *cell)
void simplemap_ff(RTLIL::Module *, RTLIL::Cell *cell)
{
FfData ff(nullptr, cell);
for (int i = 0; i < ff.width; i++) {
FfData fff = ff.slice({i});
fff.is_fine = true;
fff.emit(module, NEW_ID);
fff.emit();
}
}
passes/techmap/zinit.cc
+9 -43
View File
@@ -25,14 +25,6 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
State invert(State s) {
switch (s) {
case State::S0: return State::S1;
case State::S1: return State::S0;
default: return s;
}
}
struct ZinitPass : public Pass {
ZinitPass() : Pass("zinit", "add inverters so all FF are zero-initialized") { }
void help() override
@@ -75,45 +67,19 @@ struct ZinitPass : public Pass {
continue;
FfData ff(&initvals, cell);
if (!ff.width)
continue;
// Supporting those would require a new cell type where S has priority over R.
if (ff.has_sr)
continue;
Wire *new_q = module->addWire(NEW_ID, ff.width);
log("FF init value for cell %s (%s): %s = %s\n", log_id(cell), log_id(cell->type),
log_signal(ff.sig_q), log_signal(ff.val_init));
IdString name = cell->name;
module->remove(cell);
initvals.remove_init(ff.sig_q);
for (int i = 0; i < ff.width; i++)
if (ff.val_init[i] == State::S1)
{
if (ff.has_clk || ff.has_gclk)
ff.sig_d[i] = module->NotGate(NEW_ID, ff.sig_d[i]);
if (ff.has_aload)
ff.sig_ad[i] = module->NotGate(NEW_ID, ff.sig_ad[i]);
if (ff.has_arst)
ff.val_arst[i] = invert(ff.val_arst[i]);
if (ff.has_srst)
ff.val_srst[i] = invert(ff.val_srst[i]);
module->addNotGate(NEW_ID, SigSpec(new_q, i), ff.sig_q[i]);
ff.val_init[i] = State::S0;
}
else
{
module->connect(ff.sig_q[i], SigSpec(new_q, i));
if (all_mode)
ff.val_init[i] = State::S0;
}
ff.sig_q = new_q;
ff.emit(module, name);
pool<int> bits;
for (int i = 0; i < ff.width; i++) {
if (ff.val_init.bits[i] == State::S1)
bits.insert(i);
else if (ff.val_init.bits[i] != State::S0 && all_mode)
ff.val_init.bits[i] = State::S0;
}
ff.flip_bits(bits);
ff.emit();
}
}
}