Split up dynports.

passes/hierarchy/util/ports.cc

@@ -35,10 +35,10 @@ namespace Hierarchy {
 
 	static void build_driven_signals_index(Module *module, SigMap &sigmap, SigPool &driven_signals) {
 		for (auto cell : module->cells()) {
-			for (auto &conn : cell->connections()) {
+			for (const auto& [port, sig] : cell->connections()) {
-				if (cell->output(conn.first)) {
+				if (cell->output(port)) {
-					SigSpec sig = sigmap(conn.second);
+					SigSpec mapped_sig = sigmap(sig);
-					driven_signals.add(sig);
+					driven_signals.add(mapped_sig);
 				}
 			}
 		}
@@ -101,6 +101,29 @@ namespace Hierarchy {
 		return SigDirection::DRIVEN;
 	}
 
+	std::pair<Module*, bool> derive_blackbox_dynports(Module* module, Cell* cell, Design* design, std::set<Module*>& blackbox_derivatives) {
+		bool boxed_params = false;
+
+		if (!module->get_blackbox_attribute() || cell->parameters.empty()) {
+			return {module, boxed_params};
+		}
+
+		if (module->get_bool_attribute(ID::dynports)) {
+			IdString new_m_name = module->derive(design, cell->parameters, true);
+
+			if (new_m_name.empty())
+				return {nullptr, boxed_params};
+			if (new_m_name != module->name) {
+				module = design->module(new_m_name);
+				blackbox_derivatives.insert(module);
+			}
+		} else {
+			boxed_params = true;
+		}
+
+		return {module, boxed_params};
+	}
+
 	void check_and_adjust_ports(Module* module, std::set<Module*>& blackbox_derivatives, bool keep_portwidths, bool top_is_from_verific) {
 		Design* design = module->design;
 
@@ -111,68 +134,58 @@ namespace Hierarchy {
 			if (m == nullptr)
 				continue;
 
-			bool boxed_params = false;
+			auto [derived_m, boxed_params] = derive_blackbox_dynports(m, cell, design, blackbox_derivatives);
-			if (m->get_blackbox_attribute() && !cell->parameters.empty()) {
+			if (derived_m == nullptr)
-				if (m->get_bool_attribute(ID::dynports)) {
+				continue;
-					IdString new_m_name = m->derive(design, cell->parameters, true);
+			m = derived_m;
-					if (new_m_name.empty())
-						continue;
-					if (new_m_name != m->name) {
-						m = design->module(new_m_name);
-						blackbox_derivatives.insert(m);
-					}
-				} else {
-					boxed_params = true;
-				}
-			}
 
-			for (auto &conn : cell->connections())
+			for (const auto& [port, sig] : cell->connections())
 			{
-				Wire *w = m->wire(conn.first);
+				Wire *w = m->wire(port);
 
 				if (w == nullptr || w->port_id == 0)
 					continue;
 
-				if (GetSize(conn.second) == 0)
+				if (GetSize(sig) == 0)
 					continue;
 
-				SigSpec sig = conn.second;
+				SigSpec conn_sig = sig;
 
-				bool resize_widths = !keep_portwidths && GetSize(w) != GetSize(conn.second);
+				bool resize_widths = !keep_portwidths && GetSize(w) != GetSize(sig);
 				if (resize_widths && top_is_from_verific && boxed_params)
-					log_debug("Ignoring width mismatch on %s.%s.%s from verific, is port width parametrizable?\n",
+					log_debug("Ignoring width mismatch on %s.%s.%s from verific\n",
-							log_id(module), log_id(cell), log_id(conn.first)
+							log_id(module), log_id(cell), log_id(port)
 					);
 				else if (resize_widths) {
-					if (GetSize(w) < GetSize(conn.second))
+					if (GetSize(w) < GetSize(sig))
 					{
-						int n = GetSize(conn.second) - GetSize(w);
+						int n = GetSize(sig) - GetSize(w);
 						if (!w->port_input && w->port_output)
 						{
-							RTLIL::SigSpec out = sig.extract(0, GetSize(w));
+							RTLIL::SigSpec out = conn_sig.extract(0, GetSize(w));
-							out.extend_u0(GetSize(sig), w->is_signed);
+							out.extend_u0(GetSize(conn_sig), w->is_signed);
-							module->connect(sig.extract(GetSize(w), n), out.extract(GetSize(w), n));
+							module->connect(conn_sig.extract(GetSize(w), n), out.extract(GetSize(w), n));
 						}
-						sig.remove(GetSize(w), n);
+						conn_sig.remove(GetSize(w), n);
 					}
 					else
 					{
-						int n = GetSize(w) - GetSize(conn.second);
+						int n = GetSize(w) - GetSize(sig);
 						if (w->port_input && !w->port_output)
-							sig.extend_u0(GetSize(w), sig.is_wire() && sig.as_wire()->is_signed);
+							conn_sig.extend_u0(GetSize(w), conn_sig.is_wire() && conn_sig.as_wire()->is_signed);
 						else
-							sig.append(module->addWire(NEW_ID, n));
+							conn_sig.append(module->addWire(NEW_ID, n));
 					}
 
-					if (!conn.second.is_fully_const() || !w->port_input || w->port_output)
+					if (!sig.is_fully_const() || !w->port_input || w->port_output)
 						log_warning("Resizing cell port %s.%s.%s from %d bits to %d bits.\n", log_id(module), log_id(cell),
-								log_id(conn.first), GetSize(conn.second), GetSize(sig));
+								log_id(port), GetSize(sig), GetSize(conn_sig));
-					cell->setPort(conn.first, sig);
+					cell->setPort(port, conn_sig);
 				}
 
-				if (w->port_output && !w->port_input && sig.has_const())
+				if (w->port_output && !w->port_input && conn_sig.has_const())
 					log_error("Output port %s.%s.%s (%s) is connected to constants: %s\n",
-							log_id(module), log_id(cell), log_id(conn.first), log_id(cell->type), log_signal(sig));
+							log_id(module), log_id(cell), log_id(port), log_id(cell->type), log_signal(conn_sig));
 			}
 		}
 	}

passes/hierarchy/util/ports.h

@@ -26,6 +26,7 @@
 YOSYS_NAMESPACE_BEGIN
 
 namespace Hierarchy {
+	std::pair<Module*, bool> derive_blackbox_dynports(Module* module, Cell* cell, Design* design, std::set<Module*>& blackbox_derivatives);
 	void check_and_adjust_ports(Module* module, std::set<Module*>& blackbox_derivatives, bool keep_portwidths, bool top_is_from_verific);
 	bool resolve_connect_directionality(Module* module);
 };

passes/hierarchy/util/verilog.cc

@@ -75,8 +75,8 @@ namespace Hierarchy {
 
 					if (keep_positionals) {
 						bool found_positionals = false;
-						for (auto &conn : cell->connections())
+						for (const auto& [port, sig] : cell->connections())
-							if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9')
+							if (port[0] == '$' && '0' <= port[1] && port[1] <= '9')
 								found_positionals = true;
 						if (found_positionals)
 							continue;
@@ -109,15 +109,10 @@ namespace Hierarchy {
 					RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
 
 		// Need accurate port widths for error checking; so must derive blackboxes with dynamic port widths
-		if (submod->get_blackbox_attribute() && !cell->parameters.empty() && submod->get_bool_attribute(ID::dynports)) {
+		auto [derived_submod, boxed_params] = derive_blackbox_dynports(submod, cell, design, blackbox_derivatives);
-			IdString new_m_name = submod->derive(design, cell->parameters, true);
+		if (derived_submod == nullptr)
-			if (new_m_name.empty())
+			return;
-				return;
+		submod = derived_submod;
-			if (new_m_name != submod->name) {
-				submod = design->module(new_m_name);
-				blackbox_derivatives.insert(submod);
-			}
-		}
 
 		auto old_connections = cell->connections();
 		for (auto wire : submod->wires()) {
@@ -197,15 +192,15 @@ namespace Hierarchy {
 			if (!cell->known())
 				continue;
 
-			for (auto &conn : cell->connections())
+			for (const auto& [port, sig] : cell->connections())
 			{
-				if (!cell->output(conn.first))
+				if (!cell->output(port))
 					continue;
 
 				SigSpec new_sig;
 				bool update_port = false;
 
-				for (auto c : conn.second.chunks())
+				for (auto c : sig.chunks())
 				{
 					Wire *w = c.wire;
 
@@ -219,18 +214,18 @@ namespace Hierarchy {
 					update_port = true;
 
 					if (wand_map.count(w)) {
-						SigSpec sig = SigSpec(State::S1, GetSize(w));
+						SigSpec mapped_sig = SigSpec(State::S1, GetSize(w));
-						sig.replace(c.offset, t);
+						mapped_sig.replace(c.offset, t);
-						wand_map.at(w).append(sig);
+						wand_map.at(w).append(mapped_sig);
 					} else {
-						SigSpec sig = SigSpec(State::S0, GetSize(w));
+						SigSpec mapped_sig = SigSpec(State::S0, GetSize(w));
-						sig.replace(c.offset, t);
+						mapped_sig.replace(c.offset, t);
-						wor_map.at(w).append(sig);
+						wor_map.at(w).append(mapped_sig);
 					}
 				}
 
 				if (update_port)
-					cell->setPort(conn.first, new_sig);
+					cell->setPort(port, new_sig);
 			}
 		}