luke/yosys
1
0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-22 14:17:27 +02:00
Code Issues Packages Projects Releases Wiki Activity

Refactoring: Renamed RTLIL::Module::cells to cells_

Browse Source
This commit is contained in:
Clifford Wolf
2014-07-27 01:51:45 +02:00
parent f9946232ad
commit 4c4b602156
61 changed files with 152 additions and 152 deletions
Download Patch File Download Diff File Expand all files Collapse all files
passes/techmap/extract.cc
+3 -3
View File
@@ -182,7 +182,7 @@ namespace
std::map<std::pair<RTLIL::Wire*, int>, int> sig_use_count;
if (max_fanout > 0)
for (auto &cell_it : mod->cells)
for (auto &cell_it : mod->cells_)
{
RTLIL::Cell *cell = cell_it.second;
if (!sel || sel->selected(mod, cell))
@@ -196,7 +196,7 @@ namespace
}
// create graph nodes from cells
for (auto &cell_it : mod->cells)
for (auto &cell_it : mod->cells_)
{
RTLIL::Cell *cell = cell_it.second;
if (sel && !sel->selected(mod, cell))
@@ -253,7 +253,7 @@ namespace
}
// mark external signals (used in non-selected cells)
for (auto &cell_it : mod->cells)
for (auto &cell_it : mod->cells_)
{
RTLIL::Cell *cell = cell_it.second;
if (sel && !sel->selected(mod, cell))