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Refactoring: Renamed RTLIL::Module::cells to cells_

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This commit is contained in:
Clifford Wolf
2014-07-27 01:51:45 +02:00
parent f9946232ad
commit 4c4b602156
61 changed files with 152 additions and 152 deletions
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passes/cmds/add.cc
+1 -1
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@@ -62,7 +62,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
if (!flag_global)
return;
for (auto &it : module->cells)
for (auto &it : module->cells_)
{
if (design->modules.count(it.second->type) == 0)
continue;