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Refactoring: Renamed RTLIL::Module::cells to cells_
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@@ -47,7 +47,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
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SigMap sigmap(module);
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int cell_counter = 0, conn_counter = 0, nc_counter = 0;
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for (auto &cell_it : module->cells)
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for (auto &cell_it : module->cells_)
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{
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RTLIL::Cell *cell = cell_it.second;
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fprintf(f, "X%d", cell_counter++);
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