mirror of https://github.com/YosysHQ/yosys.git
kernel: add SwitchRule signal_src
(cherry picked from commit 53585db9f7)
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parent
cbf9b0b5d4
commit
4985df71cb
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@ -694,6 +694,7 @@ struct AST_INTERNAL::ProcessGenerator
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sw->module = current_module;
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sw->module = current_module;
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set_src_attr(sw, ast);
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set_src_attr(sw, ast);
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sw->signal = ast->children[0]->genWidthRTLIL(width_hint, sign_hint, &subst_rvalue_map.stdmap());
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sw->signal = ast->children[0]->genWidthRTLIL(width_hint, sign_hint, &subst_rvalue_map.stdmap());
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sw->signal_src = current_module->design->twines.add(Twine{ast->children[0]->loc_string()});
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current_case->switches.push_back(sw);
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current_case->switches.push_back(sw);
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for (auto &attr : ast->attributes) {
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for (auto &attr : ast->attributes) {
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@ -2557,6 +2557,7 @@ struct RTLIL::SwitchRule : public RTLIL::AttrObject
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RTLIL::Module *module = nullptr;
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RTLIL::Module *module = nullptr;
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RTLIL::SigSpec signal;
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RTLIL::SigSpec signal;
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TwineRef signal_src = Twine::Null;
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std::vector<RTLIL::CaseRule*> cases;
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std::vector<RTLIL::CaseRule*> cases;
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~SwitchRule();
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~SwitchRule();
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