End of file fix

tests/simple/aes_kexp128.v

@@ -21,4 +21,3 @@ always @(posedge clk) begin
 end
 
 endmodule
-

tests/simple/arraycells.v

@@ -12,4 +12,3 @@ module aoi12(a, b, c, y);
 	output y;
 	assign y = ~((a & b) | c);
 endmodule
-

tests/simple/attrib01_module.v

@@ -18,4 +18,3 @@ module attrib01_foo(clk, rst, inp, out);
 
   attrib01_bar bar_instance (clk, rst, inp, out);
 endmodule
-

tests/simple/attrib02_port_decl.v

@@ -22,4 +22,3 @@ module attrib02_foo(clk, rst, inp, out);
 
   attrib02_bar bar_instance (clk, rst, inp, out);
 endmodule
-

tests/simple/attrib03_parameter.v

@@ -25,4 +25,3 @@ module attrib03_foo(clk, rst, inp, out);
 
   attrib03_bar # (.WIDTH(8)) bar_instance (clk, rst, inp, out);
 endmodule
-

tests/simple/attrib04_net_var.v

@@ -29,4 +29,3 @@ module attrib04_foo(clk, rst, inp, out);
 
   attrib04_bar bar_instance (clk, rst, inp, out);
 endmodule
-

tests/simple/attrib05_port_conn.v.DISABLED

@@ -18,4 +18,3 @@ module attrib05_foo(clk, rst, inp, out);
 
   attrib05_bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out);
 endmodule
-

tests/simple/attrib06_operator_suffix.v

@@ -20,4 +20,3 @@ module attrib06_foo(clk, rst, inp_a, inp_b, out);
 
   attrib06_bar bar_instance (clk, rst, inp_a, inp_b, out);
 endmodule
-

tests/simple/attrib07_func_call.v.DISABLED

@@ -18,4 +18,3 @@ module attri07_foo(clk, rst, inp_a, inp_b, out);
     else     out <= attrib07_do_add (* combinational_adder *) (inp_a, inp_b);
 
 endmodule
-

tests/simple/attrib08_mod_inst.v

@@ -19,4 +19,3 @@ module attrib08_foo(clk, rst, inp, out);
   (* my_module_instance = 99 *)
   attrib08_bar bar_instance (clk, rst, inp, out);
 endmodule
-

tests/simple/attrib09_case.v

@@ -23,4 +23,3 @@ module attrib09_foo(clk, rst, inp, out);
 
   attrib09_bar bar_instance (clk, rst, inp, out);
 endmodule
-

tests/simple/dff_different_styles.v

@@ -101,5 +101,3 @@ always @(posedge clk, posedge preset, posedge clear) begin
 		q <= d;
 end
 endmodule
-
-

tests/simple/fsm.v

@@ -66,4 +66,3 @@ begin
 end
 
 endmodule
-

tests/simple/hierarchy.v

@@ -24,4 +24,3 @@ assign y2 = b;
 assign y3 = c;
 assign y4 = d;
 endmodule
-

tests/simple/i2c_master_tests.v

@@ -59,4 +59,3 @@ module i2c_test02(clk, slave_wait, clk_cnt, cmd, cmd_stop, cnt);
 	    cmd_stop <= #1 cmd;
 
 endmodule
-

tests/simple/loops.v

@@ -76,4 +76,3 @@ begin
 end
 
 endmodule
-

tests/simple/mem_arst.v

@@ -38,4 +38,3 @@ module MyMem #(
   end
 
 endmodule
-

tests/simple/memory.v

@@ -317,4 +317,3 @@ module memtest13 (
 		end
 	end
 endmodule
-

tests/simple/muxtree.v

@@ -80,4 +80,3 @@ module select_leaves(input R, C, D, output reg Q);
 		else
 			Q <= Q ? Q : D ? D : Q;
 endmodule
-

tests/simple/omsp_dbg_uart.v

@@ -31,4 +31,3 @@ assign cmd_valid = (uart_state==RX_CMD) & xfer_done;
 assign xfer_done = uart_state!=RX_SYNC;
 
 endmodule
-

tests/simple/paramods.v

@@ -50,4 +50,3 @@ output [width-1:0] out;
 assign out = in + step;
 
 endmodule
-

tests/simple/process.v

@@ -81,4 +81,3 @@ end else begin
 end
 
 endmodule
-

tests/simple/rotate.v

@@ -45,4 +45,3 @@ end
 endfunction
 
 endmodule
-

tests/simple/specify.v

@@ -28,4 +28,3 @@ specparam c=1:2:3;
 endspecify
 
 endmodule
-

tests/simple/usb_phy_tests.v

@@ -33,4 +33,3 @@ always @*
    end
 
 endmodule
-

tests/simple/values.v

@@ -41,4 +41,3 @@ always @*
 	endcase
 
 endmodule
-

tests/simple/vloghammer.v

@@ -79,4 +79,3 @@ endmodule
 //   output signed [5:0] y;
 //   assign y = -(5'd27);
 // endmodule
-