mirror of https://github.com/YosysHQ/yosys.git
update pass
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@ -42,9 +42,9 @@ struct AnnotateFfWidthPass : public Pass {
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// Loop through all flip-flops and annotate with their width
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int annotated = 0;
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for (auto module : design->selected_modules()) {
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for (auto cell : module->selected_cells()) {
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if (!cell->is_builtin_ff())
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for (auto module : design->modules()) {
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for (auto cell : module->cells()) {
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if (!RTLIL::builtin_ff_cell_types().count(cell->type))
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continue;
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int width;
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if (cell->hasParam(ID::WIDTH))
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@ -57,7 +57,7 @@ struct AnnotateFfWidthPass : public Pass {
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annotated++;
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}
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}
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log("Annotated %d flip-flop / latch cells.\n", annotated);
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log("Annotated %d flip-flops.\n", annotated);
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}
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} AnnotateFfWidthPass;
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PRIVATE_NAMESPACE_END
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