mirror of https://github.com/YosysHQ/yosys.git
Run toposort in both directions for better results
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@ -524,8 +524,11 @@ struct WreduceWorker
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unified_toposort.analyze_loops = false;
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unified_toposort.sort();
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// Process cells and wires together in unified topological order
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for (auto name : unified_toposort.sorted) {
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// Process cells and wires together in unified topological order (both forwards and backwards)
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std::vector<IdString> sorted_cells_and_wires_both_ways;
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sorted_cells_and_wires_both_ways.insert(sorted_cells_and_wires_both_ways.end(), unified_toposort.sorted.begin(), unified_toposort.sorted.end());
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sorted_cells_and_wires_both_ways.insert(sorted_cells_and_wires_both_ways.end(), unified_toposort.sorted.rbegin(), unified_toposort.sorted.rend());
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for (auto name : sorted_cells_and_wires_both_ways) {
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Cell *c = module->cell(name);
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Wire *w = module->wire(name);
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@ -11,7 +11,7 @@ prep
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design -save gold
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alumacc
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opt_clean
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select -assert-count 2 t:$macc_v2
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select -assert-count 1 t:$macc_v2
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maccmap -unmap
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design -copy-from gold -as gold gate
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equiv_make gold gate equiv
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