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Docs: Reflow line length

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Krystine Sherwin
2024-10-15 07:23:45 +13:00
parent 829e02ec5b
commit 40ba92e956
20 changed files with 782 additions and 785 deletions
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docs/source/using_yosys/synthesis/abc.rst
+5 -6
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@@ -10,13 +10,12 @@ fine-grained optimisation and LUT mapping.
Yosys has two different commands, which both use this logic toolbox, but use it
in different ways.
The `abc` pass can be used for both ASIC (e.g. :yoscrypt:`abc
-liberty`) and FPGA (:yoscrypt:`abc -lut`) mapping, but this page will focus on
FPGA mapping.
The `abc` pass can be used for both ASIC (e.g. :yoscrypt:`abc -liberty`) and
FPGA (:yoscrypt:`abc -lut`) mapping, but this page will focus on FPGA mapping.
The `abc9` pass generally provides superior mapping quality due to
being aware of combination boxes and DFF and LUT timings, giving it a more
global view of the mapping problem.
The `abc9` pass generally provides superior mapping quality due to being aware
of combination boxes and DFF and LUT timings, giving it a more global view of
the mapping problem.
.. _ABC: https://github.com/berkeley-abc/abc