mirror of https://github.com/YosysHQ/yosys.git
selected cells and modules
This commit is contained in:
parent
1b707c61f7
commit
3d8f4999d6
|
|
@ -42,8 +42,8 @@ struct AnnotateFfWidthPass : public Pass {
|
|||
|
||||
// Loop through all flip-flops and annotate with their width
|
||||
int annotated = 0;
|
||||
for (auto module : design->modules()) {
|
||||
for (auto cell : module->cells()) {
|
||||
for (auto module : design->selected_modules()) {
|
||||
for (auto cell : module->selected_cells()) {
|
||||
if (!RTLIL::builtin_ff_cell_types().count(cell->type))
|
||||
continue;
|
||||
int width;
|
||||
|
|
|
|||
Loading…
Reference in New Issue