mirror of https://github.com/YosysHQ/yosys.git
guard for multiple drivers
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@ -74,6 +74,7 @@ struct RegRenameInstance {
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// Map of old bits to new bits of a renamed reg wire
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// Map of old bits to new bits of a renamed reg wire
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dict<SigBit, SigBit> bit_map;
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dict<SigBit, SigBit> bit_map;
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pool<SigBit> claimed_bits;
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// Caches of target wires and wires to remove
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// Caches of target wires and wires to remove
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dict<IdString, Wire*> targetWireCache;
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dict<IdString, Wire*> targetWireCache;
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@ -168,15 +169,32 @@ struct RegRenameInstance {
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if (targetWire == oldWire)
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if (targetWire == oldWire)
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continue;
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continue;
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// Record the mapping for each bit of the old wire to the target wire.
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int normalizedIndex = bitIndex - wireOffset;
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// Check for conflicts with other cells (multiple drivers guard)
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bool conflict = false;
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for (int i = 0; i < GetSize(oldWire); i++) {
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if (claimed_bits.count(SigBit(targetWire, normalizedIndex + i))) {
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conflict = true;
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break;
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}
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}
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if (conflict) {
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log_warning("Skipping cell %s: target %s[%d] already driven by another cell\n",
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log_id(cell->name), wireName.c_str(), bitIndex);
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continue;
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}
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// Record the mapping for each bit of the old wire to the target wire.
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if (debug)
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if (debug)
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log("Connecting %s to %s[%d]\n",
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log("Connecting %s to %s[%d]\n",
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log_id(oldWire), wireName.c_str(), bitIndex);
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log_id(oldWire), wireName.c_str(), bitIndex);
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for (int i = 0; i < GetSize(oldWire); i++) {
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// Record the mapping for each bit of the old wire to the target wire.
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SigBit target(targetWire, normalizedIndex + i);
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// Translate HDL bit index to RTLIL (0-based) index by subtracting wireOffset.
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bit_map[SigBit(oldWire, i)] = target;
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int normalizedIndex = bitIndex - wireOffset;
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claimed_bits.insert(target);
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for (int i = 0; i < GetSize(oldWire); i++)
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}
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bit_map[SigBit(oldWire, i)] = SigBit(targetWire, normalizedIndex + i);
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wireRemoveCache.insert(oldWire);
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wireRemoveCache.insert(oldWire);
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}
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}
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}
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}
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