Added Testcase for bug1206

2026-07-09 08:24:19 +02:00 · 2026-07-09 08:24:19 +02:00 · 3adb423e9e
parent b88b73a99a
commit 3adb423e9e
1 changed files with 6 additions and 0 deletions
--- a/tests/rtlil/bug1206.ys
+++ b/tests/rtlil/bug1206.ys
@ -0,0 +1,6 @@
+logger -expect error "Wire width .* out of range" 1
+read_rtlil <<EOT
+module \foo
+	wire width 1073741824 \bar
+end
+EOT