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synth_gowin: remove classic ABC mapping

This commit is contained in:
Lofty 2026-08-10 12:58:29 +01:00
parent 737560c471
commit 3a148d7633
1 changed files with 7 additions and 22 deletions
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29
techlibs/gowin/synth_gowin.cc
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@ -84,9 +84,6 @@ struct SynthGowinPass : public ScriptPass
log(" -noflatten\n"); log(" -noflatten\n");
log(" do not flatten design before synthesis\n"); log(" do not flatten design before synthesis\n");
log("\n"); log("\n");
log(" -retime\n");
log(" run 'abc' with '-dff -D 1' options\n");
log("\n");
log(" -nowidelut\n"); log(" -nowidelut\n");
log(" do not use muxes to implement LUTs larger than LUT4s\n"); log(" do not use muxes to implement LUTs larger than LUT4s\n");
log("\n"); log("\n");
@ -96,9 +93,6 @@ struct SynthGowinPass : public ScriptPass
log(" -noalu\n"); log(" -noalu\n");
log(" do not use ALU cells\n"); log(" do not use ALU cells\n");
log("\n"); log("\n");
log(" -noabc9\n");
log(" disable use of new ABC9 flow\n");
log("\n");
log(" -no-rw-check\n"); log(" -no-rw-check\n");
log(" marks all recognized read ports as \"return don't-care value on\n"); log(" marks all recognized read ports as \"return don't-care value on\n");
log(" read/write collision\" (same result as setting the no_rw_check\n"); log(" read/write collision\" (same result as setting the no_rw_check\n");
@ -121,7 +115,7 @@ struct SynthGowinPass : public ScriptPass
} }
string top_opt, vout_file, json_file, family; string top_opt, vout_file, json_file, family;
bool retime, nobram, nolutram, flatten, nodffe, strict_gw5a_dffs, nowidelut, abc9, noiopads, noalu, no_rw_check, setundef, nodsp; bool nobram, nolutram, flatten, nodffe, strict_gw5a_dffs, nowidelut, noiopads, noalu, no_rw_check, setundef, nodsp;
void clear_flags() override void clear_flags() override
{ {
@ -129,14 +123,12 @@ struct SynthGowinPass : public ScriptPass
top_opt = "-auto-top"; top_opt = "-auto-top";
vout_file = ""; vout_file = "";
json_file = ""; json_file = "";
retime = false;
flatten = true; flatten = true;
nobram = false; nobram = false;
nodffe = false; nodffe = false;
strict_gw5a_dffs = false; strict_gw5a_dffs = false;
nolutram = false; nolutram = false;
nowidelut = false; nowidelut = false;
abc9 = true;
noiopads = false; noiopads = false;
noalu = false; noalu = false;
no_rw_check = false; no_rw_check = false;
@ -177,7 +169,7 @@ struct SynthGowinPass : public ScriptPass
continue; continue;
} }
if (args[argidx] == "-retime") { if (args[argidx] == "-retime") {
retime = true; // Removed: ABC9 does not support retiming.
continue; continue;
} }
if (args[argidx] == "-nobram") { if (args[argidx] == "-nobram") {
@ -209,11 +201,11 @@ struct SynthGowinPass : public ScriptPass
continue; continue;
} }
if (args[argidx] == "-abc9") { if (args[argidx] == "-abc9") {
// removed, ABC9 is on by default. // Removed: ABC9 is on by default.
continue; continue;
} }
if (args[argidx] == "-noabc9") { if (args[argidx] == "-noabc9") {
abc9 = false; // Removed: ABC9 can't be disabled.
continue; continue;
} }
if (args[argidx] == "-noiopads") { if (args[argidx] == "-noiopads") {
@ -330,8 +322,6 @@ struct SynthGowinPass : public ScriptPass
run("techmap -map +/techmap.v -map +/gowin/arith_map.v"); run("techmap -map +/techmap.v -map +/gowin/arith_map.v");
} }
run("opt -fast"); run("opt -fast");
if (retime || help_mode)
run("abc -dff -D 1", "(only if -retime)");
if (!noiopads || help_mode) if (!noiopads || help_mode)
run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O " run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O "
"-toutpad TBUF ~OEN:I:O -tinoutpad IOBUF ~OEN:O:I:IO", "(unless -noiopads)"); "-toutpad TBUF ~OEN:I:O -tinoutpad IOBUF ~OEN:O:I:IO", "(unless -noiopads)");
@ -361,16 +351,11 @@ struct SynthGowinPass : public ScriptPass
if (check_label("map_luts")) if (check_label("map_luts"))
{ {
run("sort"); run("sort");
if (nowidelut && abc9) { run("read_verilog -icells -lib -specify +/abc9_model.v");
run("read_verilog -icells -lib -specify +/abc9_model.v"); if (nowidelut) {
run("abc9 -maxlut 4 -W 500"); run("abc9 -maxlut 4 -W 500");
} else if (nowidelut && !abc9) { } else if (!nowidelut) {
run("abc -lut 4");
} else if (!nowidelut && abc9) {
run("read_verilog -icells -lib -specify +/abc9_model.v");
run("abc9 -maxlut 8 -W 500"); run("abc9 -maxlut 8 -W 500");
} else if (!nowidelut && !abc9) {
run("abc -lut 4:8");
} }
run("clean"); run("clean");
} }