mirror of https://github.com/YosysHQ/yosys.git
update autoscoping to ahndle fork scopes
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@ -345,8 +345,6 @@ int FstData::getWidth(fstHandle signal)
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// Auto-discover scope from FST by finding the top module
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std::string FstData::autoScope(Module *topmod) {
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log("Auto-discovering scopes from %d candidates...\n", GetSize(name_to_handle));
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std::string top = RTLIL::unescape_id(topmod->name);
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std::string scope = "";
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@ -359,41 +357,44 @@ std::string FstData::autoScope(Module *topmod) {
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}
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log("Extracted %d ports from module '%s'\n", GetSize(top2widths), top.c_str());
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// For each scope, track the number of matching ports
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dict<std::string, int> scopes2matches;
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// Use name_to_handle to get all signals from the FST file
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// Extract list of candidate scopes from name_to_handle
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pool<std::string> candidate_scopes;
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for (auto entry : name_to_handle) {
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std::string name = entry.first;
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fstHandle handle = entry.second;
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// Extract signal name and scope using '.'
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// Signal names of form '{scope}.signal_name' with scope potentially
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// having zero to multiple '.'
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size_t last_dot = name.find_last_of('.');
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if (last_dot != std::string::npos) { // no '.' means no scope/signal extraction is possible
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if (last_dot != std::string::npos) {
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std::string scope = name.substr(0, last_dot);
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std::string signal_name = name.substr(last_dot + 1);
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// Check that signal is in the top module and width matches
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if (top2widths.count(signal_name)) {
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int signal_width = getWidth(handle);
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if (signal_width == top2widths[signal_name]) {
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scopes2matches[scope]++;
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}
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}
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candidate_scopes.insert(scope);
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}
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}
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log("Auto-discovering scopes from %d candidates...\n", GetSize(candidate_scopes));
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// Find scopes with exact matches and add to array
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// Track number of exact matches for each scope, adding to results if all match
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std::vector<std::string> results;
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for (const auto& entry : scopes2matches) {
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int num_matches = entry.second;
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if (num_matches == GetSize(top2widths)) {
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std::string scope = entry.first;
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results.push_back(scope);
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for (const auto &scope_candidate : candidate_scopes) {
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int matches = 0;
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// Loop through all top-level ports
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for (auto &port : top2widths) {
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const std::string &port_name = port.first;
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int port_width = port.second;
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std::string key = scope_candidate + "." + port_name;
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auto it = name_to_handle.find(key);
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// Check the signal exists and has correct width to determine a match
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if (it != name_to_handle.end() && getWidth(it->second) == port_width) {
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matches++;
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}
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}
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// If all ports match, add to results
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if (matches == GetSize(top2widths)) {
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results.push_back(scope_candidate);
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}
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}
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// Logging results
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if (results.empty()) {
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log_warning("Could not auto-discover scope for module '%s'...\n",
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top.c_str());
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