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Support for SystemVerilog interfaces as a port in the top level module + test case

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Ruben Undheim
2018-10-20 11:58:25 +02:00
parent d9a4381012
commit 397dfccb30
9 changed files with 561 additions and 10 deletions
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tests/svinterfaces/run-test.sh
+1
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@@ -3,3 +3,4 @@
./runone.sh svinterface1
./runone.sh svinterface_at_top