mirror of https://github.com/YosysHQ/yosys.git
Fixed P1 issues
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parent
b103fdb047
commit
30950ee599
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@ -556,7 +556,9 @@ private:
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if (cells.empty())
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return;
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std::string prefix = stringf("\\uff_domain_%d", guard_idx >= 0 ? guard_idx : 0);
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std::string prefix = guard_idx >= 0
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? stringf("\\uff_domain_%d", guard_idx)
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: std::string("\\uff_domain_unclocked");
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std::string po_name = prefix + "_po";
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if (mod->wire(po_name))
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@ -569,14 +571,18 @@ private:
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for (auto cell : cells) {
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SigSpec old_q = cell->getPort(ID::Q);
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int q_width = GetSize(old_q);
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if (q_width == 0)
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if (q_width == 0) {
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ff_idx++;
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continue;
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}
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std::string pi_name = stringf("%s_ff%d_pi", prefix.c_str(), ff_idx);
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std::string q_int_name = stringf("%s_ff%d_q", prefix.c_str(), ff_idx);
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if (mod->wire(pi_name))
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if (mod->wire(pi_name)) {
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ff_idx++;
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continue;
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}
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Wire *pi_wire = mod->addWire(pi_name, q_width);
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pi_wire->port_input = true;
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