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Merge remote-tracking branch 'origin/master' into xaig_arrival

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This commit is contained in:
Eddie Hung
2019-09-02 12:13:44 -07:00
parent 4290548de3 7e8f7f4c59
commit 2fa3857963
7 changed files with 21 additions and 22 deletions
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techlibs/ecp5/cells_sim.v
+7 -6
View File
@@ -226,14 +226,15 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
parameter REGSET = "RESET";
parameter [127:0] LSRMODE = "LSR";
reg muxce;
always @(*)
wire muxce;
generate
case (CEMUX)
"1": muxce = 1'b1;
"0": muxce = 1'b0;
"INV": muxce = ~CE;
default: muxce = CE;
"1": assign muxce = 1'b1;
"0": assign muxce = 1'b0;
"INV": assign muxce = ~CE;
default: assign muxce = CE;
endcase
endgenerate
wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
techlibs/ecp5/ecp5_gsr.cc
+1 -1
View File
@@ -124,7 +124,7 @@ struct Ecp5GsrPass : public Pass {
SigBit lsr = sigmap(sig_lsr[0]);
if (!inverted_gsr.count(lsr))
continue;
cell->setParam(ID(SRMODE), Const("SYNC"));
cell->setParam(ID(SRMODE), Const("LSR_OVER_CE"));
cell->unsetPort(ID(LSR));
}