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Merge pull request #5561 from YosysHQ/emil/opt_expr-test-avoid-multiple-drivers 

opt_expr: avoid multiple drivers in test
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Emil J 2026-01-06 14:54:55 +01:00 committed by GitHub
parent 1567526954 856d455065
commit 2e1a2cfacb
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1 changed files with 23 additions and 18 deletions
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41
tests/opt/opt_expr_combined_assign.ys
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@ -1,11 +1,12 @@
read_verilog -sv <<EOT read_verilog -sv <<EOT
module opt_expr_or_test(input [3:0] i, input [7:0] j, output [8:0] o); module opt_expr_or_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0; wire[8:0] a;
initial begin initial begin
a = 8'b0;
a |= i; a |= i;
a |= j; a |= j;
end end
assign o = a; assign o = a;
endmodule endmodule
EOT EOT
proc proc
@ -17,12 +18,13 @@ select -assert-count 1 t:$or r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
design -reset design -reset
read_verilog -sv <<EOT read_verilog -sv <<EOT
module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o); module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0; wire[8:0] a;
initial begin initial begin
a += i; a = 8'b0;
a += j; a += i;
a += j;
end end
assign o = a; assign o = a;
endmodule endmodule
EOT EOT
proc proc
@ -34,12 +36,13 @@ select -assert-count 1 t:$add r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
design -reset design -reset
read_verilog -sv <<EOT read_verilog -sv <<EOT
module opt_expr_xor_test(input [3:0] i, input [7:0] j, output [8:0] o); module opt_expr_xor_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0; wire[8:0] a;
initial begin initial begin
a ^= i; a = 8'b0;
a ^= j; a ^= i;
a ^= j;
end end
assign o = a; assign o = a;
endmodule endmodule
EOT EOT
proc proc
@ -51,12 +54,13 @@ select -assert-count 1 t:$xor r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
design -reset design -reset
read_verilog -sv <<EOT read_verilog -sv <<EOT
module opt_expr_sub_test(input [3:0] i, input [7:0] j, output [8:0] o); module opt_expr_sub_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0; wire[8:0] a;
initial begin initial begin
a -= i; a = 8'b0;
a -= j; a -= i;
a -= j;
end end
assign o = a; assign o = a;
endmodule endmodule
EOT EOT
proc proc
@ -68,12 +72,13 @@ select -assert-count 1 t:$sub r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
design -reset design -reset
read_verilog -sv <<EOT read_verilog -sv <<EOT
module opt_expr_and_test(input [3:0] i, input [7:0] j, output [8:0] o); module opt_expr_and_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b11111111; wire[8:0] a;
initial begin initial begin
a &= i; a = 8'b11111111;
a &= j; a &= i;
a &= j;
end end
assign o = a; assign o = a;
endmodule endmodule
EOT EOT
proc proc