mirror of https://github.com/YosysHQ/yosys.git
adding more fast Cell accessors and small refactoring to reduce code dup
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@ -4568,19 +4568,15 @@ const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
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std::map<std::string, int> RTLIL::Cell::getParamsAsInts() const
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{
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std::map<std::string, int> result;
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for (auto ¶m : parameters) {
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std::string key = param.first.str();
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if (key.size() > 0 && key[0] == '\\')
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key = key.substr(1);
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result[key] = param.second.as_int();
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}
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for (const auto ¶m : parameters)
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result[RTLIL::unescape_id(param.first)] = param.second.as_int();
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return result;
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}
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double RTLIL::Cell::maxInputConstRatio() const
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{
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double max_ratio = 0.0;
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for (auto &conn : connections_) {
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for (const auto &conn : connections_) {
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if (input(conn.first)) {
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double ratio = conn.second.const_ratio();
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if (ratio > max_ratio)
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@ -4590,6 +4586,24 @@ double RTLIL::Cell::maxInputConstRatio() const
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return max_ratio;
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}
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std::vector<std::string> RTLIL::Cell::getOutputPortNames() const
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{
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std::vector<std::string> result;
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for (const auto &conn : connections_) {
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if (output(conn.first))
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result.push_back(RTLIL::unescape_id(conn.first));
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}
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return result;
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}
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std::map<std::string, int> RTLIL::Cell::getConnectionSizes() const
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{
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std::map<std::string, int> result;
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for (const auto &conn : connections_)
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result[RTLIL::unescape_id(conn.first)] = conn.second.size();
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return result;
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}
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void RTLIL::Cell::sort()
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{
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connections_.sort(sort_by_id_str());
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@ -2539,6 +2539,12 @@ public:
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// Returns the maximum const_ratio() across all input ports, 0.0 if no input ports
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double maxInputConstRatio() const;
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// Returns the names of all output ports (backslash-stripped)
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std::vector<std::string> getOutputPortNames() const;
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// Returns {port_name: sig.size()} for all connections, port names backslash-stripped
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std::map<std::string, int> getConnectionSizes() const;
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void sort();
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void check();
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void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false);
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