Renamed "placeholder" to "blackbox"

frontends/ast/ast.cc

@@ -720,7 +720,7 @@ static AstModule* process_module(AstNode *ast)
 				delete child;
 		}
 		ast->children.swap(new_children);
-		ast->attributes["\\placeholder"] = AstNode::mkconst_int(1, false);
+		ast->attributes["\\blackbox"] = AstNode::mkconst_int(1, false);
 	}
 
 	ignoreThisSignalsInInitial = RTLIL::SigSpec();

frontends/verilog/verilog_frontend.cc

@@ -90,7 +90,7 @@ struct VerilogFrontend : public Frontend {
 		log("        do not run the pre-processor\n");
 		log("\n");
 		log("    -lib\n");
-		log("        only create empty placeholder modules\n");
+		log("        only create empty blackbox modules\n");
 		log("\n");
 		log("    -noopt\n");
 		log("        don't perform basic optimizations (such as const folding) in the\n");