Added test cases

2026-08-22 14:17:27 +02:00 · 2022-02-16 13:27:59 +01:00
parent fb22d7cdc4
commit 271ac28b41
39 changed files with 897 additions and 0 deletions
@@ -0,0 +1,6 @@
+read_verilog adff.v
+proc
+opt_dff
+stat
+select -assert-count 1 t:$adff
+sim -clock clk -r tb_adff.fst -scope tb_adff.uut -sim-cmp adff