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Added test cases

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This commit is contained in:
Miodrag Milanovic
2022-02-16 13:27:59 +01:00
parent fb22d7cdc4
commit 271ac28b41
39 changed files with 897 additions and 0 deletions
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tests/sim/dlatch.v
+6
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module dlatch( input d, en, output reg q );
always @* begin
if ( en )
q = d;
end
endmodule